IEEE Transactions on Computers, Volume 30

Volume 30, Number 1, January 1981

• Eugen I. Muehldorf, Anil D. Savkar:
  LSI Logic Testing - An Overview. 1-17
  
• John P. Robinson, Martin Cohn:
  Counting Sequences. 17-23
  
• Mario Barbacci:
  Instruction Set Processor Specifications (ISPS): The Notation and Its Applications. 24-40
  
• Bryan D. Ackland, Neil Weste:
  The Edge Flag Algorithm - A Fill Method for Raster Scan Displays. 41-48
  
• Donald E. Thomas, Daniel P. Siewiorek:
  Measuring Designer Performance to Verify Design Automation Systems. 48-61
  
• Mark A. Franklin, Norman L. Soong:
  One-Dimensional Optimization on Multiprocessor Systems. 61-66
  
• Simeon C. Ntafos, S. Louis Hakimi:
  On Structured Digraphs and Program Testing. 67-77
  

• D. G. Maritsas, M. G. Hartley:
  Comments on "Revision of the Buffer Length Derivation for a Modified E_k/D/1 System by Maritsas and Hartley. 78
  
• Ricardo E. Suarez, Oscar Chang, Vladimir Adam:
  Design of a Dynamically Programmable Logic Gate. 79-81
  
• Gerard G. L. Meyer:
  A Fault Diagnosis Algorithm for Asymmetric Modular Architectures. 81-83
  
• Michael L. Fredman:
  Observations Concerning the Complexity of a Class of On-Line Algebraic Problems. 83-86
  

Volume 30, Number 2, February 1981

• Gavriela Freund Lev, Nicholas Pippenger, Leslie G. Valiant:
  A Fast Parallel Algorithm for Routing in Permutation Networks. 93-100
  
• David Nassimi, Sartaj Sahni:
  Data Broadcasting in SIMD Computers. 101-107
  
• Leonard R. Marino:
  General Theory of Metastable Operation. 107-115
  
• Marc Davio:
  Kronecker Products and Shuffle Algebra. 116-125
  
• André Thayse:
  P-Functions: A New Tool for the Analysis and Synthesis of Binary Programs. 126-134
  
• Leslie G. Valiant:
  Universality Considerations in VLSI Circuits. 135-140
  

• Robert D. Braun, Donald D. Givone:
  A Generalized Algorithm for Constructing Checking Sequences. 141-144
  
• Ayakannu Mathialagan, Nripendra N. Biswas:
  Bit Steering in the Minimization of Control Memory in Microprogrammed Digital Computers. 144-147
  
• Kevin Q. Brown:
  Comments on "Algorithms for Reporting and Counting Geometric Intersections". 147-148
  
• Charles B. Silio Jr., James H. Pugsley, B. Albert Jeng:
  Control Memory Wort Width Optimization Using Multiple-Valued Circuits. 148-153
  
• Dharma P. Agrawal, Krishna K. Agarwal:
  Efficient Sorting with CCD's and Magnetic Bubble Memories. 153-156
  
• J. George Shanthikumar:
  Comments on "The Buffer Behavior in Computer Communication Systems". 157
  
• Fredrick J. Hill, R. E. Swanson, M. Masud, Zainalabedin Navabi:
  Structure Specification with a Procedural Hardware Description Language. 157-161
  
• Stephen R. McConnel, Daniel P. Siewiorek:
  Synchronization and Voting. 161-164
  
• Jan Gecsei, Jean-Paul Brassard:
  The Topology of Cellular Partitioning Networks. 164-168
  

Volume 30, Number 3, March 1981

• Lawrence Snyder:
  Formal Models of Capability-Based Protection Systems. 172-181
  
• Toshihide Ibaraki, Tsunehiko Kameda, Shunichi Toida:
  On Minimal Test Sets for Locating Single Link Failures in Networks. 182-190
  
• Daniel Gajski:
  An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines. 190-206
  
• Shahid H. Bokhari:
  On the Mapping Problem. 207-214
  
• Prabhakar Goel:
  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. 215-222
  

• William F. McColl:
  Planar Crossovers. 223-225
  
• W. R. English:
  Synthesis of Finite State Algorithms in a Galois Field GF[pⁿ]. 225-229
  
• Mamoru Tanaka, Shinji Ozawa, Shinsaku Mori:
  Rewritable Progammable Logic Array of Current Mode Logic. 229-234
  
• Sung Je Hong:
  Existence Algorithms for Synchronizing/Distinguishing Sequences. 234-237
  
• A. Sengupta, D. K. Chattopadhyay, A. Palit, A. K. Bandyopadhyay, A. K. Choudhury:
  Realization of Fault-Tolerant Machines - Linear Code Application. 237-240
  
• Gerhard Wustmann:
  Comments on "Autocorrelation Function of Sequential M-Bit Words Taken from an N-Bit Shift Register (PN) Sequence". 241
  

Volume 30, Number 4, April 1981

• Ellis Horowitz, Alessandro Zorat:
  The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI. 247-253
  
• Shyue B. Wu, Ming T. Liu:
  A Cluster Structure as an Interconnection Network for Large Multimicrocomputer Systems. 254-264
  
• Larry D. Wittie:
  Communication Structures for Large Networks of Microcomputers. 264-273
  
• Daniel M. Dias, J. Robert Jump:
  Analysis and Simulation of Buffered Delta Networks. 273-282
  
• Mark A. Franklin:
  VLSI Performance Comparison of Banyan and Crossbar Communications Networks. 283-291
  

• Bruce W. Arden, Hikyu Lee:
  Analysis of Chordal Ring Network. 291-295
  
• Pen-Chung Yew, Duncan H. Lawrie:
  An Easily Controlled Network for Frequently Used Permutation. 296-298
  
• J. E. Wirsching, T. Kishi:
  CONET: A Connection Network Model. 298-301
  

Volume 30, Number 5, May 1981

• Takao Uehara, William M. van Cleemput:
  Optimal Layout of CMOS Functional Arrays. 305-312
  
• Israel Koren, Yoram Maliniak:
  On Classes of Positive, Negative, and Imaginary Radix Number Systems. 312-317
  
• Wesley W. Chu, Guy Fayolle, David G. Hibbits:
  An Analysis of a Tandem Queueing System for Flow Control in Computer Networks. 318-324
  
• Chuan-lin Wu, Tse-Yun Feng:
  The Universality of the Shuffle-Exchange Network. 324-332
  
• David Nassimi, Sartaj Sahni:
  A Self-Routing Benes Network and Parallel Permutation Algorithms. 332-340
  
• Walid A. Abu-Sufah, David J. Kuck, Duncan H. Lawrie:
  On the Performance Enhancement of Paging Systems Through Program Analysis and Transformations. 341-356
  

• Se June Hong, Daniel L. Ostapko:
  A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks. 356-358
  
• Dusan M. Kodek:
  Conditions for the Existence of Fast Number Theoretic Transforms. 359-360
  
• Neil V. Murray:
  Some Observations on Equivalence Handling Methods. 361-362
  
• Andrzej Proskurowski:
  Minimum Broadcast Trees. 363-366
  
• Patrick Shen-Pei Wang:
  Finite-Turn Repetitive Checking Automata and Sequential/Parallel Matrix Languages. 366-370
  
• Angela Y. Wu, Azriel Rosenfeld:
  SIMD Machines and Cellular d-Graph Automata. 370-372
  

Volume 30, Number 6, June 1981

• Takanobu Baba, Hiroshi Hagiwara:
  The MPG System: A Machine-Independent Efficient Microprogram Generator. 373-395
  
• D. T. Lee, Hsu Chang, C. K. Wong:
  An On-Chip Compare/Steer Bubble Sorter. 396-405
  
• Jacques Labetoulle, Guy Pujolle:
  HDLC Throughput and Response Time for Bidirectional Data Flow with Nonuniform Frame Sizes. 405-413
  
• Kyung-Yong Chwa, S. Louis Hakimi:
  On Fault Identification in Diagnosable Systems. 414-422
  
• Alice C. Parker, John J. Wallace:
  SLIDE: An I/O Hardware Descriptive Language. 423-439
  
• Makoto Imase, Masaki Itoh:
  Design to Minimize Diameter on Building-Block Network. 439-442
  

• Edward A. Snow, Daniel P. Siewiorek:
  Implementation and Performance Evaluation of Computer Families. 443-447
  
• Stephen H. Unger:
  Double-Edge-Triggered Flip-Flops. 447-451
  
• S. Prakash, V. V. Rao:
  Comments on "Very Fast Fourier Transform Algorithms Hardware for Implementation". 452
  
• Irving S. Reed, Trieu-Kien Truong, Boonsieng Benjauthrit:
  Addendum to "A New Hybrid Algorithm for Computing a Fast Discrete Fourier Transform". 453-454
  
• G. Persky, Bou Nin Tien, B. S. Ting:
  Comments on "An Optimal Solution for the Channel-Assignment Problem". 454
  
• Frank Rubin:
  Further Comments on "An Optimal Solution for the Channel-Assignment Problem". 455
  
• Ulrich Lauther:
  Additional Comments on " An Optimal Solution for the Channel-Assignment Problem". 455
  

Volume 30, Number 7, July 1981

• Scott Davidson, David Landskov, Bruce Shriver, Patrick W. Mallett:
  Some Experiments in Local Microcode Compaction for Horizontal Machines. 460-477
  
• Joseph A. Fisher:
  Trace Scheduling: A Technique for Global Microcode Compaction. 478-490
  
• Mario Tokoro, Euji Tamura, Takashi Takizuka:
  Optimization of Microprograms. 491-504
  
• John A. Stankovic:
  The Types and Interactions of Vertical Migrations of Functions in a Multilevel Interpretive System. 505-513
  

• Andries van Dam, Mario Barbacci, Constantine Halatsis, J. Joosten, M. Letheren:
  Simulation of a Horizontal Bit-Sliced Processor Using the ISPS Architecture Simulation Facility. 513-519
  
• Glenford J. Myers, David G. Hocker:
  The Use of Software Simulators in the Testing and Debugging of Microprogram Logic. 519-523
  

Volume 30, Number 8, August 1981

• Jerry R. Van Aken, Gregory L. Zick:
  The Expression Processor: A Pipelined, Multiple-Processor Architecture. 525-536
  
• Gian Carlo Bongiovanni, C. K. Wong:
  Tree Search in Major/Minor Loop Magnetic Bubble Memories. 537-545
  
• Suchai Thanawastien, Victor P. Nelson:
  Interference Analysis of Shuffle/Exchange Networks. 545-556
  
• Hideo Fujiwara:
  On Closedness and Test Complexity of Logic Circuits. 556-562
  
• Thirumalai Sridhar, John P. Hayes:
  A Functional Approach to Testing Bit-Sliced Microprocessors. 563-571
  
• Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki:
  A Layout System for the Random Logic Portion of an MOS LSI Chip. 572-581
  

• Vishwani D. Agrawal:
  An Information Theoretic Approach to Digital Fault Testing. 582-587
  
• James R. Armstrong, F. Gail Gray:
  Fault Diagnosos in a Boolean n Cube Array of Microprocessors. 587-590
  
• Jon T. Butler:
  Speed-Efficiency-Complexity Tradeoffs in Universal Diagnosis Algorithms. 590-596
  
• Alan B. Hayes:
  Stored State Asynchronous Sequential Circuits. 596-600
  
• Yashwant K. Malaiya, Stephen Y. H. Su:
  Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults. 600-604
  
• George Markowsky:
  Syndrome-Testability Can be Achieved by Circuit Modification. 604-606
  
• Jacob Savir:
  Syndrome-Testing of "Syndrome-Untestable" Combinational Circuits. 606-608
  
• Jack Worlton:
  Comments on "Parallelism and Representation Problems in Distributed Systems". 608-609
  
• Jim B. Surjaatmadja:
  An Algebra for Switching Circuits. 609-613
  

Volume 30, Number 9, September 1981

• Kenneth C. Smith:
  The Prospects for Multivalued Logic: A Technology and Applications View. 619-634
  
• Tsutomu Sasao:
  Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays. 635-643
  
• Hans G. Kerkhoff, Marius L. Tervoert:
  Multiple-Valued Logic Charge-Coupled Devices. 644-652
  
• Marc Davio, Jean-Pierre Deschamps:
  Synthesis of Discrete Functions Using I²L Technology. 653-661
  

• Tich T. Dao:
  SEC-DED Nonbinary Code for Fault-Torelant Byte-Organized Memory Implemented with Quaternary Logic. 662-666
  
• Waldo C. Kabat, Anthony S. Wojcik:
  On the Design of 4-Valued Digital Systems. 666-671
  
• A. D. Singh, F. Gail Gray, James R. Armstrong:
  Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules. 671-674
  
• Gardner Pomper, James R. Armstrong:
  Representation of Multivalued Functions Using the Direct Cover Method. 674-679
  
• Craig S. Holt, James E. Smith:
  Diagnosis of Systems with Asymmetric Invalidation. 679-690
  
• John H. Zurawski, J. B. Gosling:
  Design of High-Speed Digital Divider Units. 691-699
  

• S. Dormido, M. A. Canto:
  Synthesis of Generalized Parallel Counters. 699-703
  

Volume 30, Number 10, October 1981

• David Gelernter:
  A DAG-Based Algorithm for Prevention of Store-and-Forward Deadlock in Packet Networks. 709-715
  
• Douglas W. Clark, Butler W. Lampson, Kenneth A. Pier:
  The Memory System of a High-Performance Personal Computer. 715-733
  
• Simon S. Lam, Y. C. Luke Lien:
  Congestion Control of Packet Communication Networks by Input Buffer Limits - A Simulation Study. 733-742
  
• Tse-Yun Feng, Chuan-lin Wu:
  Fault-Diagnosis for a Class of Multistage Interconnection Networks. 743-758
  
• Nai-Kuan Tsao:
  Error Complexity Analysis of Algorithms for Matrix Multiplication and Matrix Chain Product. 758-771
  
• Janak H. Patel:
  Performance of Processor-Memory Interconnections for Multiprocessors. 771-780
  
• J. George Shanthikumar:
  On the Buffer Behavior with Poisson Arrivals, Priority Service, and Random Server Interruptions. 781-786
  
• C. V. Ramamoorthy, Benjamin W. Wah:
  An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor. 787-800
  
• Bulent I. Dervisoglu, Donald J. Criscione:
  A Hard Progammable Control Unit Design Using VLSI Technology. 800-810
  

• Takeo Kanai:
  An Improvement of Reliability of Memory System with Skewing Reconfiguration. 811-812
  
• Allan Gottlieb:
  Comments on "Concurrent Search and Insertion in AVL Trees". 812
  
• C. V. Ramamoorthy, Benjamin W. Wah:
  The Degradation in Memory Utilization Due to Dependencies. 813-818
  

Volume 30, Number 11, November 1981

• Hideo Fujiwara, Kozo Kinoshita:
  A Design of Programmable Logic Arrays with Universal Tests. 823-828
  
• Wilfried Daehn, Joachim Mucha:
  A Hardware Approach to Self-Testing of Large Programmable Logic Arrays. 829-833
  
• R. Parthasarathy, Sudhakar M. Reddy:
  A Testable Design of Iterative Logic Arrays. 833-841
  
• Thirumalai Sridhar, John P. Hayes:
  Design of Easily Testable Bit-Sliced Systems. 842-854
  
• Vinod K. Agarwal, Andy S. F. Fung:
  Multiple Fault Testing of Large Circuits by Single Fault Test Sets. 855-865
  
• Edward J. McCluskey, Saied Bozorgui-Nesbat:
  Design for Autonomous Test. 866-875
  
• Jacob A. Abraham, Daniel Gajski:
  Design of Testable Structures Defined by Simple Loops. 875-884
  
• Robert W. Priester, James B. Clary:
  New Measures of Testability and Test Complexity for Linear Analog Failure Analysis. 884-888
  
• V. Visvanathan, Alberto L. Sangiovanni-Vincentelli:
  Diagnosability of Nonlinear Circuits and Systems - Part I: The dc Case. 889-898
  
• Richard Saeks, Alberto L. Sangiovanni-Vincentelli, V. Visvanathan:
  Diagnosability of Nonlinear Circuits and Systems - Part II: Dynamical Systems. 899-904
  

Volume 30, Number 12, December 1981

• Taylor L. Booth: In Memoriam: Richard E. Merwin (1922-1981). 909
• David Avis, Godfried T. Toussaint:
  An Optimal Algorithm for Determining the Visibility of a Polygon from an Edge. 910-914
  
• Gita Gopal, J. W. Wong:
  Delay Analysis of Broadcast Routing in Packet-Switching Networks. 915-922
  
• James R. Goodman, Carlo H. Séquin:
  Hypertree: A Multiprocessor Interconnection Topology. 923-933
  
• Howard Jay Siegel, Leah J. Siegel, Frederick C. Kemmerer, Philip T. Mueller Jr., Harold E. Smalley, S. Diane Smith:
  PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition. 934-947
  
• Mark G. Karpovsky:
  An Approach for Error Detection and Error Correction in Distributed Systems Computing Numerical Functions. 947-953
  
• Stephen M. Walters, F. Gail Gray, Richard A. Thompson:
  Self-Diagnosing Cellular Implementations of Finite-State Machines. 953-959
  
• Raphael A. Finkel, Marvin H. Solomon:
  The Lens Interconnection Strategy. 960-965
  
• Yih-Chyun Jenq:
  Digital Convolution Algorithm for Pipelining Multiprocessor Systems. 966-973
  

• Sharad C. Seth, K. Narayanaswamy:
  A Graph Model for Pattern-Sensitive Faults in Random Access Memories. 973-977
  
• David Steinberg, Michael Rodeh:
  A Layout for the Shuffle-Exchange Network with O(N²/log^3/2N) Area. 977-982
  
• Dong S. Suk, Sudhakar M. Reddy:
  A March Test for Functional Faults in Semiconductor Random Access Memories. 982-985
  
• S. L. Hurst:
  Comments on "Design of a Dynamically Programmable Logic Gate". 986-988
  
• Chi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya:
  Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits. 989-995
  
• Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith:
  The Weighted Syndrome Sums Approach to VLSI Testing. 996-1000
  

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