Volume 57-II, Number 1, January 2010
Ping Gui, Zheng Gao, Chen-Wei Huang, Liming Xiu: The Effects of Flying-Adder Clocks on Digital-to-Analog Converters. 1-5- Mohamed Helaoui, Fadhel M. Ghannouchi: Linearization of Power Amplifiers Using the Reverse MM-LINC Technique. 6-10
- Mu-Chen Huang, Shen-Iuan Liu: A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing. 11-15
- He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. 16-20
- Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen: Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment. 21-25
- Chen-Fong Hsiao, Yuan Chen, Chen-Yi Lee: A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors. 26-30
- Chua-Chin Wang, Chia-Hao Hsu, Chi-Chun Huang, Jun-Han Wu: A Self-Disabled Sensing Technique for Content-Addressable Memories. 31-35
- Chengde Zheng, Huaguang Zhang, Zhanshan Wang: Improved Robust Stability Criteria for Delayed Cellular Neural Networks via the LMI Approach. 41-45
- Maoyin Chen: Synchronization in Complex Dynamical Networks With Random Sensor Delay. 46-50
- Jun Lin, Jin Sha, Zhongfeng Wang, Li Li: An Efficient VLSI Architecture for Nonbinary LDPC Decoders. 51-55
- Abdelali El Aroudi, Mohamed Orabi: Stabilizing Technique for AC-DC Boost PFC Converter Based on Time Delay Feedback. 56-60
- Zheng Zhang, Ngai Wong: Passivity Test of Immittance Descriptor Systems Based on Generalized Hamiltonian Methods. 61-65
Volume 57-II, Number 2, February 2010
- Ian Galton: Why Dynamic-Element-Matching DACs Work. 69-74
- Jean-Michel Redoute, Michiel Steyaert: Kuijk Bandgap Voltage Reference With High Immunity to EMI. 75-79
- Edward N. Y. Ho, Philip K. T. Mok: A Capacitor-Less CMOS Active Feedback Low-Dropout Regulator With Slew-Rate Enhancement for Portable On-Chip Application. 80-84
- Hyunchol Shin, Youngcho Kim: A CMOS Active-RC Low-Pass Filter With Simultaneously Tunable High- and Low-Cutoff Frequencies for IEEE 802.22 Applications. 85-89
- Zhenbiao Li, Ming Li, Dong Zhao, Dequn Ma, Wenhai Ni, Zhongming Ouyang: TD-SCDMA/HSDPA Transceiver and Analog Baseband Chipset in 0.18- μħbox m CMOS Process. 90-94
- Alexander Vaz, Aritz Ubarretxena, Ibon Zalbide, Daniel Pardo, Héctor Solar, Andrés Garcia-Alonso, Roc Berenguer: Full Passive UHF Tag With a Temperature Sensor Suitable for Human Body Temperature Monitoring. 95-99
- Nathan Schemm, Sina Balkir, Michael W. Hoffman: A 4-muhboxW CMOS Front End for Particle Detection Applications. 100-104
- João P. Oliveira, João Goes, Michael Figueiredo, Edinei Santin, João Fernandes, J. Ferreira: An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification. 105-109
- Junjie Yao, Jin Liu, Hoi Lee: Bulk Voltage Trimming Offset Calibration for High-Speed Flash ADCs. 110-114
- Young-Ho Kwak, Inhwa Jung, Chulwoo Kim: A ħbox Gb/s+ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time. 120-125
- Chi-Chun Huang, Tzung-Je Lee, Wei-Chih Chang, Chua-Chin Wang: (1/3) times hboxVDD-to- (3/2) times hboxVDD Wide-Range I/O Buffer Using 0.35- muhboxm 3.3-V CMOS Technology. 126-130
- Tomaso Poggi, Francesco Comaschi, Marco Storace: Digital Circuit Realization of Piecewise-Affine Functions With Nonuniform Resolution: Theory and FPGA Implementation. 131-135
- Chao-Ming Chen, Chien-Chang Hung, Yuan-Hao Huang: An Energy-Efficient Partial FFT Processor for the OFDMA Communication System. 136-140
- Kwok-Wo Wong, Qiuzhen Lin, Jianyong Chen: Simultaneous Arithmetic Coding and Encryption Using Chaotic Maps. 146-150
Volume 57-II, Number 3, March 2010
- Gordon W. Roberts, Mohammed Ali-Bakhshian: A Brief Introduction to Time-to-Digital and Digital-to-Time Converters. 153-157
- Shanthi Pavan: Systematic Design Centering of Continuous Time Oversampling Converters. 158-162
- Jin-Fu Lin, Soon-Jyh Chang, Chun-Cheng Liu, Chih-Hao Huang: A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique. 163-167
- Chun-Hsien Kuo, Tai-Haur Kuo, Kow-Liang Wen: Bias-and-Input Interchanging Technique for Cyclic/Pipelined ADCs With Opamp Sharing. 168-172
- Jaemo Yang, Choul-Young Kim, Dong-Wook Kim, Songcheol Hong: Design of a 24-GHz CMOS VCO With an Asymmetric-Width Transformer. 173-177
- Shih-Yuan Kao, Shen-Iuan Liu: A 1.62/2.7-Gb/s Adaptive Transmitter With Two-Tap Preemphasis Using a Propagation-Time Detector. 178-182
- Pavel Poliakov, Ankur Anchlia, Marie Garcia Bardon, Bram Rooseleer, Bart De Wachter, Nadine Collaert, Koen van der Zanden, Wim Dehaene, Diederik Verkest, Miguel Corbalan Miranda: Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM. 183-187
- Taejoong Song, Jongmin Park, Sang Min Lee, Jaehyouk Choi, Kihong Kim, Chang-Ho Lee, Kyutae Lim, Joy Laskar: A 122-mW Low-Power Multiresolution Spectrum-Sensing IC With Self-Deactivated Partial Swing Techniques. 188-192
- Jaimin Mehta, Vasile Zoicas, Oren Eliezer, Robert Bogdan Staszewski, Sameh Rezeq, Mitch Entezari, Poras T. Balsara: An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter. 193-197
- Tso-Bing Juang, Chin-Chieh Chiu, Ming-Yu Tsai: Improved Area-Efficient Weighted Modulo 2n + 1 Adder Design With Simple Correction Schemes. 198-202
- Raj S. Katti, Rajesh G. Kavasseri, Vyasa Sai: Pseudorandom Bit Generation Using Coupled Congruential Generators. 203-207
- Subho Chatterjee, Sayeef Salahuddin, Saibal Mukhopadhyay: Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes. 208-212
- Antonio Loría: Master-Slave Synchronization of Fourth-Order Lü Chaotic Oscillators via Linear Output Feedback. 213-217
- Abdelali El Aroudi, Enric Rodriguez, Ramon Leyva, Eduard Alarcón: A Design-Oriented Combined Approach for Bifurcation Prediction in Switched-Mode Power Converters. 218-222
- Ricardo Riaza: Nondegeneracy Conditions for Active Memristive Circuits. 223-227
- Hye-Yoon Joo, Lee-Sup Kim: A Data-Pattern-Tolerant Adaptive Equalizer Using the Spectrum Balancing Method. 228-232
- Liang Li, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo: An Energy-Efficient Error Correction Scheme for IEEE 802.15.4 Wireless Sensor Networks. 233-237
- Hoi Lee, Seong-Ryong Ryu: An Efficiency-Enhanced DCM Buck Regulator With Improved Switching Timing of Power Transistors. 238-242
Volume 57-II, Number 4, April 2010
- Socheat Heng, Cong-Kha Pham: A Low-Power High-PSRR Low-Dropout Regulator With Bulk-Gate Controlled Circuit. 245-249
- Annajirao Garimella, M. Wasequr Rashid, Paul M. Furth: Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO. 250-254
- Chi-En Liu, Yi-Jhan Hsieh, Jean-Fu Kiang: RFID Regulator Design Insensitive to Supply Voltage Ripple and Temperature Variation. 255-259
- Mehdi Kiani, Maysam Ghovanloo: An RFID-Based Closed-Loop Wireless Power Transmission System for Biomedical Applications. 260-264
- Chua-Chin Wang, Chih-Lin Chen, Ron-Chi Kuo, Doron Shmilovitz: Self-Sampled All-MOS ASK Demodulator for Lower ISM Band Applications. 265-269
- Nitesh Singhal, Sudhakar Pamarti: A Digital Envelope Combiner for Switching Power Amplifier Linearization. 270-274
- Gordana Jovanovic-Dolecek, Massimiliano Laddomada: An Economical Class of Droop-Compensated Generalized Comb Filters: Analysis and Design. 275-279
- Gabriel Torrens, Bartomeu Alorda, Salvador Barcelo, José Luis Rosselló, Sebastiàn A. Bota, Jaume Segura: Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination. 280-284
- Pramod Kumar Meher: LUT Optimization for Memory-Based Computation. 285-289
- Stuart N. Wooters, Benton H. Calhoun, Travis N. Blalock: An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS. 290-294
- Alexandru Amaricai, Mircea Vladutiu, Oana Boncalo: Design Issues and Implementations for Floating-Point Divide-Add Fused. 295-299
- Xi Chen, Siu Chung Wong, Chi Kong Tse: Adding Randomness to Modeling Internet TCP-RED Systems With Interactive Gateways. 300-304
- Alexander Jimenez Triana, Wallace Kit-Sang Tang, Guanrong Chen, Alain Gauthier: Chaos Control in Duffing System Using Impulsive Parametric Perturbations. 305-309
- Rui Wang, Bo Wang, Guo-Ping Liu, Wei Wang, David Rees: Hinfty Controller Design for Networked Predictive Control Systems Based on the Average Dwell-Time Approach. 310-314
Volume 57-II, Number 5, May 2010
- Vladimir Stojanovic, Chih-Kong Ken Yang, Ron Ho: Guest Editorial for Special Issue on High-Performance Multichip Interconnections. 317-318
- Shih-Yuan Kao, Shen-Iuan Liu: A 20-Gb/s Transmitter With Adaptive Preemphasis in 65-nm CMOS Technology. 319-323
- Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, Ying-Fu Lin: A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications. 324-328
- Ahmed Nassar, Ahmed Emira, Ahmed Nader Mohieldin, Ahmed Hussien Khalil: Multichannel Clock and Data Recovery: A Synchronous Approach. 329-333
- Farshid Aryanfar, Amir Amirkhany: A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces. 339-342
- Arun Palaniappan, Samuel Palermo: Power Efficiency Comparisons of Interchip Optical Interconnect Architectures. 343-347
- Jung-Won Han, Boo-Young Choi, Mikyung Seo, Jisook Yun, Dongmyung Lee, Taewook Kim, Yunseong Eo, Sung Min Park: A 20-Gb/s Transformer-Based Current-Mode Optical Receiver in 0.13- μħbox m CMOS. 348-352
- Won Namgoong, Lei Feng: Digital Processing of Single-Carrier Cyclic Prefixed Frequency Channelized Receiver for Serial Links. 353-358
- Rajan Narasimha, Naresh R. Shanbhag: Design of Energy-Efficient High-Speed Links via Forward Error Correction. 359-363
- Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli: Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands. 364-368
- Meng-Hung Shen, Jen-Huan Tsai, Po-Chiun Huang: Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC. 369-373
- Lucas Andrew Milner, Gabriel A. Rincón-Mora: A Feedforward 10times CMOS Current-Ripple Suppressor for Switching Power Supplies. 374-378
- Young Hun Seo, Young-Sang Kim, Hong-June Park, Jae-Yoon Sim: A 5 Gb/s Transmitter With a TDR-Based Self-Calibration of Preemphasis Strength. 379-383
- Karun Rawat, Meenakshi Rawat, Fadhel M. Ghannouchi: Compensating I-Q Imperfections in Hybrid RF/Digital Predistortion With an Adapted Lookup Table Implemented in an FPGA. 389-393
- Roger Yubtzuan Chen, Zong-Yi Yang: Modeling the High-Frequency Degradation of Phase/Frequency Detectors. 394-398
Volume 57-II, Number 6, June 2010
- Gabor C. Temes: Micropower Data Converters: A Tutorial. 405-410
- Sungho Lee, Sangwook Nam: A CMOS Outphasing Power Amplifier With Integrated Single-Ended Chireix Combiner. 411-415
- Bart De Vuyst, Pieter Rombouts, Jeroen De Maeyer, Georges G. E. Gielen: The Nyquist Criterion: A Useful Tool for the Robust Design of Continuous-Time SigmaDelta Modulators. 416-420
- Lei Wang, Leibo Liu, Hongyi Chen: An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL. 421-425
- Hannu Olkkonen, Juuso T. Olkkonen: Sampling and Reconstruction of Transient Signals by Parallel Exponential Filters. 426-429
- Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, An-Yeu Wu: A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm. 430-434
- Jong-Min Baek, Jung-Hoon Chun, Kee-Won Kwon: A Power-Efficient Voltage Upconverter for Embedded EEPROM Application. 435-439
- Shien-Chun Luo, Lih-Yih Chiou: A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing. 440-445
- Song-Nien Tang, Jui-Wei Tsai, Tsin-Yuan Chang: A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications. 451-455
- Du-Qu Wei, Bo Zhang, Dong Yuan Qiu, Xiao-Shu Luo: Effects of Current Time-Delayed Feedback on the Dynamics of a Permanent-Magnet Synchronous Motor. 456-460
- Zongbo Xie, Jiuchao Feng: Blind Source Separation of Continuous-Time Chaotic Signals Based on Fast Random Search Algorithm. 461-465
- Andrzej Borys: Consideration of Volterra Series With Excitation and/or Impulse Responses in the Form of Dirac Impulses. 466-470
- François Auger: Some New Developments on the Al-Alaoui and the Pei and Hsu s-to-z Transforms. 471-475
- Wutao Yin, Aryan Saadat Mehr: A Variable Regularization Method for Affine Projection Algorithm. 476-480
- G. P. Liu: Predictive Controller Design of Networked Systems With Communication Delays and Data Loss. 481-485
- Yanbo Gao, Guoping Lu, Zhiming Wang: Passivity Analysis of Uncertain Singularly Perturbed Systems. 486-490
Volume 57-II, Number 7, July 2010
- Jeffrey S. Walling, David J. Allstot: Linearizing CMOS Switching Power Amplifiers Using Supply Regulators. 497-501
- Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon: A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique. 502-506
- Tejinder Singh Sandhu, Kamal El-Sankary, Ezz I. El-Masry: A Distortion-Compensated Charge Transfer Amplifier for a 1.66-MHz Cyclic Pipeline ADC. 507-511
- Heather Orser, Anand Gopinath: A 20 GS/s 1.2 V 0.13 muhboxm CMOS Switched Cascode Track-and-Hold Amplifier. 512-516
- Min C. Park, Michael H. Perrott, Robert Bogdan Staszewski: A Time-Domain Resolution Improvement of an RF-DAC. 517-521
- Chin-Lung Yang, Shin-Yi Shu, Yi-Chyun Chiang: Design of a K-Band Chip Filter With Three Tunable Transmission Zeros Using a Standard 0.13-muhboxm CMOS Technology. 522-526
- Toru Tanzawa: A Behavior Model of a Dickson Charge Pump Circuit for Designing a Multiple Charge Pump System Distributed in LSIs. 527-530
- Alex K. Y. Wong, Ka Nang Leung, Kong-Pang Pun, Yuan-Ting Zhang: A 0.5-Hz High-Pass Cutoff Dual-Loop Transimpedance Amplifier for Wearable NIR Sensing Device. 531-535
- Chih-Jung Chen, Tah-Hsiung Chu, Chih-Lung Lin, Zeui-Chown Jou: A Study of Loosely Coupled Coils for Wireless Power Transfer. 536-540
- Rajeev K. Dokania, Xiao Wang, Siddharth G. Tallur, Carlos I. Dorta-Quinones, Alyssa B. Apsel: An Ultralow-Power Dual-Band UWB Impulse Radio. 541-545
- Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee: A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators. 546-550
- Honggang Qi, Qingming Huang, Wen Gao: A Low-Cost Very Large Scale Integration Architecture for Multistandard Inverse Transform. 551-555
- Won Namgoong: Flicker Noise in Observer-Controller Digital PLL. 556-560
- Hyunbean Yi, Sandip Kundu, Sangwook Cho, Sungju Park: A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains. 561-565
- Cheng-Chi Wong, Hsie-Chia Chang: Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System. 566-570
- Sheau-Fang Lei, Shin-Chi Lai, Po-Yin Cheng, Ching-Hsing Luo: Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms. 571-575
Volume 57-II, Number 8, August 2010
- Yannis P. Tsividis: Event-Driven Data Acquisition and Digital Signal Processing - A Tutorial. 577-581
- Kuang-Chi He, Ming-Tsung Li, Chen-Ming Li, Jenn-Hwan Tarng: Parallel-RC Feedback Low-Noise Amplifier for UWB Applications. 582-586
- Md. Mahbub Reja, Kambiz K. Moez, Igor M. Filanovsky: An Area-Efficient Multistage 3.0- to 8.5-GHz CMOS UWB LNA Using Tunable Active Inductors. 587-591
- Sleiman Ball Sleiman, Mohammed Ismail: Multimode Reconfigurable Digital SigmaDelta Modulator Architecture for Fractional-N PLLs. 592-596
- Gang-Neng Sung, Szu-Chia Liao, Jian-Ming Huang, Yu-Cheng Lu, Chua-Chin Wang: All-Digital Frequency Synthesizer Using a Flying Adder. 597-601
- Kailash Chandrashekar, Marco Corsi, John Fattaruso, Bertan Bakkaloglu: A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling. 602-606
- U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti: Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. 607-611
- Chua-Chin Wang, Ron-Chi Kuo, Jen-Wei Liu: 0.9 V to 5 V Bidirectional Mixed-Voltage I/O Buffer With an ESD Protection Output Stage. 612-616
- Xiaoman Wang, Baoyong Chi, Zhihua Wang: A Low-Power High-Data-Rate ASK IF Receiver With a Digital-Control AGC Loop. 617-621
- Francisco Colodro Ruiz, Antonio Jesús Torralba Silgado: Spectral Analysis of Pulsewidth-Modulated Sampled Signals. 622-626
- Dong Wang, Milos D. Ercegovac, Nanning Zheng: Design of High-Throughput Fixed-Point Complex Reciprocal/Square-Root Unit. 627-631
- Ji-Woong Choi, Jungwon Lee, Byung Gueon Min, Jongsun Park: Energy Efficient Hardware Architecture of LU Triangularization for MIMO Receiver. 632-636
- Shih-Chang Hsia, Wen-Hsien Liao: Forward Computations for Context-Adaptive Variable-Length Coding Design. 637-641
- Patrick Yin Chiang, Changhui Hu: Chaotic Pulse-Position Baseband Modulation for an Ultra-Wideband Transceiver in CMOS. 642-646
- Shin-Chi Lai, Wen-Ho Juang, Chia-Lin Chang, Chen-Chieh Lin, Ching-Hsing Luo, Sheau-Fang Lei: Low-Computation-Cycle, Power-Efficient, and Reconfigurable Design of Recursive DFT for Portable Digital Radio Mondiale Receiver. 647-651
- Sanghoon Park, Lawrence E. Larson, Laurence B. Milstein: An RF Receiver Detection Technique for Cognitive Radio Coexistence. 652-656
Volume 57-II, Number 9, September 2010
- Jung-Yu Chang, Shen-Iuan Liu: A Phase-Locked Loop With Background Leakage Current Compensation. 666-670
- Salvatore Levantino, Luca Collamati, Carlo Samori, Andrea L. Lacaita: Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division. 671-675
- Vikas Singh, Nagendra Krishnapura, Shanthi Pavan: Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time DeltaSigma Modulators. 676-680
- Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: A 1-muhboxW 600- hboxppm/circhboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits. 681-685
- Chen Zheng, Dongsheng Ma: Design of Monolithic Low Dropout Regulator for Wireless Powered Brain Cortical Implants Using a Line Ripple Rejection Technique. 686-690
- Hyunjoong Lee, Jong-Kwan Woo, Hyo-Jin Nam, Won-Hyeog Jin, Moongi Jeong, Young-Sik Kim, Jin-Koog Shin, Suhwan Kim: Charge Amplifier With an Enhanced Frequency Response for SPM-Based Data Storage. 691-695
- M. N. S. Swamy: Transpose of a Multiterminal Element and Applications. 696-700
- Liang Liu, Fan Ye, Xiaojing Ma, Tong Zhang, Junyan Ren: A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology. 701-705
- Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding. 706-710
- Shin-Chi Lai, Sheau-Fang Lei, Wen-Ho Juang, Ching-Hsing Luo: A Low-Cost, Low-Complexity, and Memory-Free Architecture of Novel Recursive DFT and IDFT Algorithms for DTMF Application. 711-715
- Md. Ashraful Islam, Khan A. Wahid: Area- and Power-Efficient Design of Daubechies Wavelet Transforms Using Folded AIQ Mapping. 716-720
- Sven Lütkemeier, Ulrich Rückert: A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror. 721-724
- Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi: Multiple Error Detection in DNA Self-Assembly Using Coded Tiles. 725-729
- B. Liao, Z. G. Zhang, S. C. Chan: A New Robust Kalman Filter-Based Subspace Tracking Algorithm in an Impulsive Noise Environment. 740-744
- Goran Molnar, Mladen Vucic: Noncausal IIR Fractional Hilbert Transformers With Equiripple or Flat Phase Response. 745-749
- Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan: Passive Rational Interpolation-Based Reduction via Carathéodory Extension for General Systems. 750-755
Volume 57-II, Number 10, October 2010
- Pui Ying Or, Ka Nang Leung: A Fast-Transient Low-Dropout Regulator With Load-Tracking Impedance Adjustment and Loop-Gain Boosting Technique. 757-761
- Indika U. K. Bogoda Appuhamylage, Shunsuke Okura, Toru Ido, Kenji Taniguchi: An Area-Efficient CMOS Bandgap Reference Utilizing a Switched-Current Technique. 762-766
- Xin Ming, Ying-qian Ma, Ze-kun Zhou, Bo Zhang: A High-Precision Compensated CMOS Bandgap Voltage Reference Without Resistors. 767-771
- Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys: Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication. 777-781
- Xiaoheng Chen, Shu Lin, Venkatesh Akella: QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders. 782-786
- Xinmiao Zhang, Jiangli Zhu: Algebraic Soft-Decision Decoder Architectures for Long Reed-Solomon Codes. 787-792
- Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi: Resistive-Type CVNS Distributed Neural Networks With Improved Noise-to-Signal Ratio. 793-797
- Kyung Ki Kim, Wei Wang, Ken Choi: On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits. 798-802
- Simin Yu, Jinhu Lu, Guanrong Chen, Xinghuo Yu: Design and Implementation of Grid Multiwing Butterfly Chaotic Attractors From a Piecewise Lorenz System. 803-807
- Chia-Ling Wei, Chun-Hsien Wu, Lu-Yao Wu, Ming-Hsien Shih: An Integrated Step-Up/Step-Down DC-DC Converter Implemented With Switched-Capacitor Circuits. 813-817
- Mohammad A. Al-Shyoukh, Hoi Lee: A Compact Fully-Integrated Extremum-Selector-Based Soft-Start Circuit for Voltage Regulators in Bulk CMOS Technologies. 818-822
- Guoyong Shi: Computational Complexity Analysis of Determinant Decision Diagram. 828-832
Volume 57-II, Number 11, November 2010
- Paschalis Simitsakis, Yannis Papananos, Eleni-Sotiria Kytonaki: Design of a Low Voltage-Low Power 3.1-10.6 GHz UWB RF Front-End in a CMOS 65 nm Technology. 833-837
- Javad Javidan, Mojtaba Atarodi, Howard C. Luong: High Power Amplifier Based on a Transformer-Type Power Combiner in CMOS Technology. 838-842
- Shuenn-Yuh Lee, Liang-Hung Wang, Yu-Heng Lin: A CMOS Quadrature VCO With Subharmonic and Injection-Locked Techniques. 843-847
- Joseph Hamilton, Shouli Yan, T. R. Viswanathan: A Discrete-Time Input Delta Sigma ADC Architecture Using a Dual-VCO-Based Integrator. 848-852
- Bei Peng, Hao Li, Seung-Chul Lee, Pingfen Lin, Yun Chiu: A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion. 853-857
- Marko Neitola, Timo Rahkonen, Janne Raappana: A Qualification Approach to DAC Mismatch-Shaping Methods. 858-862
- Juan M. Carrillo, Guido Torelli, Miguel Angel Domínguez, Raquel Pérez-Aloe, José M. Valverde, J. Francisco Duque-Carrillo: A Family of Low-Voltage Bulk-Driven CMOS Continuous-Time CMFB Circuits. 863-867
- Amit P. Patel, Gabriel A. Rincón-Mora: High Power-Supply-Rejection (PSR) Current-Mode Low-Dropout (LDO) Regulator. 868-873
- Hung-Yu Wang, Wen-Chung Huang, Nan-Hui Chiang: Symbolic Nodal Analysis of Circuits Using Pathological Elements. 874-877
- Bongsub Song, Nayeon Cho, Byunghoon Kim, Jung-Han Choi, Young-Lok Kim, Jinwook Burm: An Autofocus Sensor With Global Shutter Using Offset-Free Frame Memory. 878-882
- Ahmed Shahein, Mohamed Afifi, Markus Becker, Niklas Lotze, Yiannos Manoli: A Power-Efficient Tunable Narrow-Band Digital Front End for Bandpass Sigma-Delta ADCs in Digital FM Receivers. 883-887
- Yen-Jen Chang: Using the Dynamic Power Source Technique to Reduce TCAM Leakage Power. 888-892
- Kevin Cushon, Camille Leroux, Saied Hemati, Shie Mannor, Warren J. Gross: A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding. 893-897
- Ming Li, Chi Kong Tse, Herbert H. C. Iu, Xikui Ma: Unified Equivalent Modeling for Stability Analysis of Parallel-Connected DC/DC Converters. 898-902
- Phatiphat Thounthong, Serge Pierfederici: A New Control Law Based on the Differential Flatness Principle for Multiphase Interleaved DC-DC Converter. 903-907
- Yun-Bo Zhao, Guo-Ping Liu, David Rees: Actively Compensating for Data Packet Disorder in Networked Control Systems. 913-917
Volume 57-II, Number 12, December 2010
- Ehab Ahmed Sobhy, Sebastian Hoyos: A Multiphase Multipath Technique With Digital Phase Shifters for Harmonic Distortion Cancellation. 921-925
- Omeed Momeni, Hossein Hashemi, Ehsan Afshari: A 10-Gb/s Inductorless Transimpedance Amplifier. 926-930
- Gary J. Ballantyne, Jifeng Geng: Effect of Reference Clock Jitter and Demonstration of Near Image-Free Operation for the ADPLL. 931-935
- Wu-Hsin Chen, Maciej E. Inerowicz, Byunghoo Jung: Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition. 936-940
- Stefan Tertinek, James P. Gleeson, Orla Feely: Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter. 941-945
- Fang-Ren Liao, Shey-Shi Lu: A Programmable Edge-Combining DLL With a Current-Splitting Charge Pump for Spur Suppression. 946-950
- Shu-Yu Hsu, Jui-Yuan Yu, Chen-Yi Lee: A Sub-10-muhboxW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications. 951-955
- Shunsuke Okura, Hajime Shibata, Tetsuro Okura, Toru Ido, Kenji Taniguchi: A Frequency Model of a Continuously Driven Clocked CMOS Comparator. 956-960
- Bei Peng, Hao Li, Pingfen Lin, Yun Chiu: An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs. 961-965
- Mohamed Aboudina, Behzad Razavi: A New DAC Mismatch Shaping Technique for Sigma-Delta Modulators. 966-970
- Alaa I. Abunjaileh, Ian C. Hunter: Direct Synthesis of Parallel-Connected Symmetrical Two-Port Filters. 971-974
- Ivo Petras: Fractional-Order Memristor-Based Chua's Circuit. 975-979
- Meng-Fan Chang, Yung-Chi Chen, Chien-Fu Chen: A 0.45-V 300-MHz 10T Flowthrough SRAM With Expanded write/ read Stability and Speed-Area-Wise Array for Sub-0.5-V Chips. 980-985
- Sangho Shin, Kyungmin Kim, Sung-Mo Kang: Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices. 986-990
- Mariano Fons, Francisco Fons, Enrique Cantó: Fingerprint Image Processing Acceleration Through Run-Time Reconfigurable Hardware. 991-995
- Shih-Liang Chen, TingTing Hwang, Wen-Wei Lin: Randomness Enhancement Using Digitalized Modified Logistic Map. 996-1000
- Shilian Wang, Xiaodong Wang: M-DCSK-Based Chaotic Communications in MIMO Multipath Channels With No Channel State Information. 1001-1005
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last updated on 2013-06-19T203413 by the dblp team