IEEE Transactions on Circuits and Systems - Part II: Express Briefs, Volume 58-II

Volume 58-II, Number 1, January 2011

• Wei-Hsin Tseng, Jieh-Tsorng Wu, Yung-Cheng Chu:
  A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero. 1-5
  
• Brian Fitzgibbon, Michael Peter Kennedy:
  Calculation of Cycle Lengths in Higher Order Error Feedback Modulators With Constant Inputs. 6-10
  
• Jui-Yi Lin, Hwann-Kaeo Chiou:
  Power-Constrained Third-Order Active Notch Filter Applied in IR-LNA for UWB Standards. 11-15
  
• Shinichi Hori, Boris Murmann:
  Feedforward Interference Cancellation Architecture for Short-Range Wireless Communication. 16-20
  
• José M. Algueta Miguel, Carlos Aristoteles De la Cruz-Blas, Antonio J. López-Martín:
  Fully Differential Current-Mode CMOS Triode Translinear Multiplier. 21-25
  
• Yikai Wang, M. Koen, Dongsheng Ma:
  Low-Noise CMOS TGC Amplifier With Adaptive Gain Control for Ultrasound Imaging Receivers. 26-30
  
• Rafal Dlugosz, Tomasz Talaska, Witold Pedrycz:
  Current-Mode Analog Adaptive Mechanism for Ultra-Low-Power Neural Networks. 31-35
  
• Qiaoyan Yu, Paul Ampadu:
  A Dual-Layer Method for Transient and Permanent Error Co-Management in NoC Links. 36-40
  
• Dakshina Murthy-Bellur, Marian K. Kazimierczuk:
  Isolated Two-Transistor Zeta Converter With Reduced Transistor Voltage Stress. 41-45
  
• Håkan Johansson:
  Farrow-Structure-Based Reconfigurable Bandpass Linear-Phase FIR Filters for Integer Sampling Rate Conversion. 46-50
  
• Xiaoping Lai, Zhiping Lin, Hon Keung Kwan:
  A Sequential Minimization Procedure for Minimax Design of IIR Filters Based on Second-Order Factor Updates. 51-55
  
• Tsung-Hsien Liu, Jin-Yi Jiang, Yuan-Sun Chu:
  A Low-Cost MMSE-SIC Detector for the MIMO System: Algorithm and Hardware Implementation. 56-61
  

Volume 58-II, Number 2, February 2011

• Ching-Yuan Yang, Chih-Hsiang Chang, Jun-Hong Weng, Hsin-Ming Wu:
  A 0.5/0.8-V 9-GHz Frequency Synthesizer With Doubling Generation in 0.13- μħbox m CMOS. 65-69
  
• Young Hun Seo, Seon-Kyoo Lee, Jae-Yoon Sim:
  A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18- μħbox m CMOS. 70-74
  
• Rahul Singh, Yves Audet, Yves Gagnon, Yvon Savaria, Étienne Boulais, Michel Meunier:
  A Laser-Trimmed Rail-to-Rail Precision CMOS Operational Amplifier. 75-79
  
• Man Kay Law, Amine Bermak, Chao Shi:
  A Low-Power Energy-Harvesting Logarithmic CMOS Image Sensor With Reconfigurable Resolution Using Two-Level Quantization Scheme. 80-84
  
• Arthur Spivak, Alexander Belenky, Alexander Fish, Orly Yadid-Pecht:
  A Wide-Dynamic-Range CMOS Image Sensor With Gating for Night Vision Systems. 85-89
  
• Dong-Yong Shin, Hyunjoong Lee, Suhwan Kim:
  A Delta-Sigma Interface Circuit for Capacitive Sensors With an Automatically Calibrated Zero Point. 90-94
  
• Chun-Fu Liao, Yuan-Hao Huang:
  Power-Saving 4 ˟ 4 Lattice-Reduction Processor for MIMO Detection With Redundancy Checking. 95-99
  
• Aaron E. Cohen, Keshab K. Parhi:
  Secure Variable Data Rate Transmission. 100-104
  
• Ching-Che Chung, Cheng-Ruei Yang:
  An Autocalibrated All-Digital Temperature Sensor for On-Chip Thermal Monitoring. 105-109
  
• Jianyong Chen, Junwei Zhou, Kwok-Wo Wong:
  A Modified Chaos-Based Joint Compression and Encryption Scheme. 110-114
  
• Massimiliano Laddomada, D. E. Troncoso, Gordana Jovanovic-Dolecek:
  Design of Multiplierless Decimation Filters Using an Extended Search of Cyclotomic Polynomials. 115-119
  
• S. C. Chan, Z. G. Zhang, Y. J. Chu:
  A New Transform-Domain Regularized Recursive Least M-Estimate Algorithm for a Robust Linear Estimation. 120-124
  

Volume 58-II, Number 3, March 2011

• José M. Muñoz-Ferreras, Roberto Gómez-Garcia, Félix Pérez-Martínez:
  RF Front-End Concept and Implementation for Direct Sampling of Multiband Signals. 129-133
  
• Jun Wu, Peichen Jiang, Dongpo Chen, Jianjun Zhou:
  A Dual-Band GNSS RF Front End With a Pseudo-Differential LNA. 134-138
  
• Chao-Ching Hung, Shen-Iuan Liu:
  A Noise Filtering Technique for Fractional-N Frequency Synthesizers. 139-143
  
• Wu-Hsin Chen, Byunghoo Jung:
  High-Speed Low-Power True Single-Phase Clock Dual-Modulus Prescalers. 144-148
  
• Ching-Che Chung, Chiun-Yao Ko, Sung-En Shen:
  Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology. 149-153
  
• Federico Bizzarri, Angelo Brambilla, Giancarlo Storti Gajani:
  Phase Noise Simulation in Analog Mixed Signal Circuits: An Application to Pulse Energy Oscillators. 154-158
  
• Armin Tajalli, Yusuf Leblebici:
  Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter. 159-163
  
• Cristina Azcona, Belén Calvo, Nicolás J. Medrano-Marqués, Alberto Bayo, Santiago Celma:
  12-b Enhanced Input Range On-Chip Quasi-Digital Converter With Temperature Compensation. 164-168
  
• Manho Kim, Hyunjoong Lee, Jong-Kwan Woo, Nan Xing, Min-Oh Kim, Suhwan Kim:
  A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching. 169-173
  
• Marco Ho, Ka Nang Leung:
  Dynamic Bias-Current Boosting Technique for Ultralow-Power Low-Dropout Regulator in Biomedical Applications. 174-178
  
• G. S. Visweswaran, Pragya Varshney, Maneesha Gupta:
  New Approach to Realize Fractional Power in z-Domain at Low Frequency. 179-183
  
• Yimin Zhou, Yu Sun, Zhidan Feng, Shixin Sun:
  PID-Based Bit Allocation Strategy for H.264/AVC Rate Control. 184-188
  

Volume 58-II, Number 4, April 2011

• Peng Wei, Wenyi Che, Zhongyu Bi, Chen Wei, Yan Na, Li Qiang, Min Hao:
  High-Efficiency Differential RF Front-End for a Gen2 RFID Tag. 189-194
  
• Mury Thian, Vincent F. Fusco:
  Transmission-Line Class-E Power Amplifier With Extended Maximum Operating Frequency. 195-199
  
• Davide Tasca, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
  Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL. 200-204
  
• Nagendra Krishnapura, Abhishek Agrawal, Sameer Singh:
  A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps. 205-209
  
• Zuow-Zun Chen, Tai-Cheng Lee:
  The Study of a Dual-Mode Ring Oscillator. 210-214
  
• Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Jyun-Neng Chen:
  A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications. 215-219
  
• Hyeong-Ju Kang, Seung Jae Lee, Byung-Do Yang:
  Area-Efficient Prefilter Architecture for a CDMA Receiver. 220-224
  
• Evgueni Doukhnitch, Emre Ozen:
  Hardware-Oriented Algorithm for Quaternion-Valued Matrix Decomposition. 225-229
  
• Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
  Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. 230-234
  
• David Wolpert, Paul Ampadu:
  A Sensor System to Detect Positive and Negative Current-Temperature Dependences. 235-239
  
• Julien Clinton Sprott:
  A New Chaotic Jerk Circuit. 240-243
  
• Yuan-Ta Hsieh, Bin-Da Liu, Jian-Fu Wu, Chiao-Li Fang, Hann-Huei Tsai, Ying-Zong Juang:
  A High Current Accuracy Boost White LED Driver Based on Offset Calibration Technique. 244-248
  

Volume 58-II, Number 5, May 2011

• Jae Jin Lee, Chul Soon Park:
  60-GHz Gigabits-Per-Second OOK Modulator With High Output Power in 90-nm CMOS. 249-253
  
• Eleni-Sotiria Kytonaki, Yannis Papananos:
  A Low-Voltage Differentially Tuned Current-Adjusted 5.5-GHz Quadrature VCO in 65-nm CMOS Technology. 254-258
  
• Aliakbar Ghadiri, Kambiz K. Moez:
  Compact Transformer-Based Distributed Amplifier for UWB Systems. 259-263
  
• Mincheol Seo, Kyungwon Kim, Min-Su Kim, Hyungchul Kim, Jeongbae Jeon, Myung-Kyu Park, Hyojoon Lim, Youngoo Yang:
  Ultrabroadband Linear Power Amplifier Using a Frequency-Selective Analog Predistorter. 264-268
  
• Jong-Hoon Kim, Jung-Bum Shin, Jae-Yoon Sim, Hong-June Park:
  5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump. 269-273
  
• Chang-Seob Shin, Gil-Cho Ahn:
  A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique. 274-278
  
• Sandhya Purighalla, Brent Maundy:
  84-dB Range Logarithmic Digital-to-Analog Converter in CMOS 0.18- muhboxm Technology. 279-283
  
• Shanthi Pavan:
  On Continuous-Time DeltaSigma Modulators With Return-to-Open DACs. 284-288
  
• Jingcheng Zhuang, Bruce Andrew Doyle, Emerson S. Fang:
  Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End. 289-293
  
• Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
  Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. 294-298
  
• Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye:
  An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion. 299-303
  
• Hou-Jen Ko, Shen-Fu Hsiao:
  Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding. 304-308
  
• Kyun-Sang Park, Jong-Tae Lim:
  Stability Analysis of Nonstandard Nonlinear Singularly Perturbed Discrete Systems. 309-313
  
• Simin Yu, Jinhu Lu, Guanrong Chen, Xinghuo Yu:
  Generating Grid Multiwing Chaotic Attractors by Constructing Heteroclinic Loops Into Switching Systems. 314-318
  

Volume 58-II, Number 6, June 2011

• Chao-Ching Hung, Shen-Iuan Liu:
  A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm. 321-325
  
• Liming Xiu, Ming Lin, Hong Jiang:
  A Storage-Based Carry Randomization Technique for Spurs Reduction in Flying-Adder Frequency Synthesizer. 326-330
  
• Stefan Tertinek, Orla Feely:
  Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter. 331-335
  
• Tsutomu Tanzawa:
  A Switch-Resistance-Aware Dickson Charge Pump Model for Optimizing Clock Frequency. 336-340
  
• Marko Neitola, Timo Rahkonen:
  Predicting and Avoiding Spurious Tones in a DWA-Mismatch-Shaping DAC. 341-345
  
• Nan Sun:
  High-Order Mismatch-Shaping in Multibit DACs. 346-350
  
• Esther Rodríguez-Villegas, Alexander J. Casson, Phil Corbishley:
  A Subhertz Nanopower Low-Pass Filter. 351-355
  
• Indrit Myderrizi, Shahram Minaei, Erkan Yüce:
  An Electronically Fine-Tunable Multi-Input-Single-Output Universal Filter. 356-360
  
• Won-Young Lee, Lee-Sup Kim:
  A Spread Spectrum Clock Generator for DisplayPort Main Link. 361-365
  
• Constantin Paleologu, Jacob Benesty, Silviu Ciochina:
  Regularization of the Affine Projection Algorithm. 366-370
  
• Raveendranatha P. Mahesh, A. Prasad Vinod:
  A Low-Complexity Flexible Spectrum-Sensing Scheme for Mobile Cognitive Radio Terminals. 371-375
  
• Chen Zheng, Dongsheng Ma:
  Design of a Monolithic Automatic Substrate/Supply Multiplexer for DVS-Enabled Adaptive Power Converters. 376-380
  
• Zbigniew Galias, Xinghuo Yu:
  Study of Periodic Solutions in Discretized Two-Dimensional Sliding-Mode Control Systems. 381-385
  
• Yanbo Gao, Binghua Sun, Guoping Lu:
  Passivity-Based Integral Sliding-Mode Control of Uncertain Singularly Perturbed Systems. 386-390
  

Volume 58-II, Number 7, July 2011

• Qun Jane Gu, Heng-Yu Jian, Zhiwei Xu, Yi-Cheng Wu, Mau-Chung Frank Chang, Yves Baeyens, Young-Kai Chen:
  CMOS Prescaler(s) With Maximum 208-GHz Dividing Speed and 37-GHz Time-Interleaved Dual-Injection Locking Range. 393-397
  
• Viet-Hoang Le, Hoai-Nam Nguyen, In-Young Lee, Seok-Kyun Han, Sang-Gug Lee:
  A Passive Mixer for a Wideband TV Tuner. 398-401
  
• Pere Gilabert, Gabriel Montoro, Eduard Bertran:
  FPGA Implementation of a Real-Time NARMA-Based Digital Adaptive Predistorter. 402-406
  
• Jia Hao Cheong, Kok Lim Chan, Pradeep Basappa Khannur, Kei Tee Tiew, Minkyu Je:
  A 400-nW 19.5-fJ/Conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18- muhboxm CMOS. 407-411
  
• Junhua Shen, Peter R. Kinget:
  Current-Charge-Pump Residue Amplification for Ultra-Low-Power Pipelined ADCs. 412-416
  
• Taehwan Oh, Nima Maghari, David Gubbins, Un-Ku Moon:
  Analysis of Residue Integration Sampling With Improved Jitter Immunity. 417-421
  
• Jun-Yong Song, Oh-Kyong Kwon:
  Clock- and Data-Recovery Circuit With Independently Controlled Eye-Tracking Loop for High-Speed Graphic DRAMs. 422-426
  
• Nikola Zaric, Nedjeljko Lekic, Srdjan Stankovic:
  An Implementation of the L-Estimate Distributions for Analysis of Signals in Heavy-Tailed Noise. 427-431
  
• Kanwen Wang, Jialin Chen, Wei Cao, Ying Wang, Lingli Wang, Jiarong Tong:
  A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design. 432-436
  
• Chien-Chen Lin, Yao Li, Chen-Yi Lee:
  A Predefined Bit-Plane Comparison Coding for Mobile Video Applications. 437-441
  
• Sangho Shin, Kyosun Kim, Sung-Mo Kang:
  Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations. 442-446
  
• Mohammad Saleh Tavazoei:
  On Monotonic and Nonmonotonic Step Responses in Fractional Order Systems. 447-451
  
• Bin Zhou, Guang-Ren Duan, Zongli Lin:
  On Semiglobal Stabilization of Discrete-Time Periodic Systems With Bounded Controls. 452-456
  

Volume 58-II, Number 8, August 2011

• Hyun H. Boo, SungWon Chung, Joel L. Dawson:
  Digitally Assisted Feedforward Compensation of Cartesian-Feedback Power-Amplifier Systems. 457-461
  
• Jiangtao Xu, Carlos E. Saavedra, Guican Chen:
  An Active Inductor-Based VCO With Wide Tuning Range and High DC-to-RF Power Efficiency. 462-466
  
• Davide Ponton, Gerhard Knoblinger, Andreas Roithmeier, Frederico Cernoia, Marc Tiebout, Michael Fulde, Pierpaolo Palestri:
  LC-VCO in the 3.3- to 4-GHz Band Implemented in 32-nm Low-Power CMOS Technology. 467-471
  
• Sudip Shekhar, Daibashish Gangopadhyay, Eum Chan Woo, David J. Allstot:
  A 2.4-GHz Extended-Range Type-I SigmaDelta Fractional-N Synthesizer With 1.8-MHz Loop Bandwidth and -110-dBc/Hz Phase Noise. 472-476
  
• Mi-Jo Kim, Lee-Sup Kim:
  A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications. 477-481
  
• Hongrui Wang, Lei Zhang, Li Zhang, Yan Wang, Zhiping Yu:
  Design of 24-GHz High-Gain Receiver Front-End Utilizing ESD-Split Input Matching Network. 482-486
  
• Chang-Lin Hsieh, Shen-Iuan Liu:
  A 1-16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector. 487-491
  
• Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang, Yu-Liang Li, Yong-Jhen Jhu:
  A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler. 492-496
  
• Jingcheng Zhuang:
  Low-Blind-Period Differential Sampler for High-Speed Serial Link Receivers. 497-501
  
• Ko-Chi Kuo, Chi-Wei Wu:
  A Switching Sequence for Linear Gradient Error Compensation in the DAC Design. 502-506
  
• Paolo Stefano Crovetti:
  Finite Common-Mode Rejection in Fully Differential Nonlinear Circuits. 507-511
  
• Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro:
  Structural DMR: A Technique for Implementation of Soft-Error-Tolerant FIR Filters. 512-516
  
• Chih-Peng Fan, Chia-Hao Fang, Chia-Wei Chang, Shun-Ji Hsu:
  Fast Multiple Inverse Transforms With Low-Cost Hardware Sharing Design for Multistandard Video Decoding. 517-521
  
• Youngjoo Lee, Hoyoung Yoo, In-Cheol Park:
  Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization. 522-526
  
• Mahmoudreza Babaei, Hamed Ghasemieh, Mahdi Jalili:
  Cascading Failure Tolerance of Modular Small-World Networks. 527-531
  
• Said Boussakta, Monir Taha Hamood:
  Rader-Brenner Algorithm for Computing New Mersenne Number Transform. 532-536
  
• M. Zulfiquar A. Bhotto, Andreas Antoniou:
  Robust Quasi-Newton Adaptive Filtering Algorithms. 537-541
  

Volume 58-II, Number 9, September 2011

• Shreyas Sen, Farshid Aryanfar, Carl Werner:
  A Multiband Transceiver System in 45-nm CMOS for Extended Data Rate through Notchy Wireline Channels. 545-549
  
• Chi-Sheng Lin, Ting-Hsu Chien, Chin-Long Wey:
  A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process. 550-554
  
• Yu Song, Zeljko Ignjatovic:
  A High-Performance PLL With a Low-Power Active Switched-Capacitor Loop Filter. 555-559
  
• Doo-Chan Lee, Kyu-Young Kim, Young-Jae Min, Jongsun Park, Soo-Won Kim:
  A Jitter and Power Analysis on DCO. 560-564
  
• Chunyuan Zhou, Lei Zhang, Li Zhang, Yan Wang, Zhiping Yu, He Qian:
  Injection-Locking-Based Power and Speed Optimization of CML Dividers. 565-569
  
• Martina Mincica, Domenico Pepe, Domenico Zito:
  CMOS UWB Multiplier. 570-574
  
• Costas Laoudias, Costas Psychalinos:
  1.5-V Complex Filters Using Current Mirrors. 575-579
  
• Victor R. Gonzalez-Diaz, Fabio Pareschi, Gianluca Setti, Franco Maloberti:
  A Pseudorandom Number Generator Based on Time-Variant Recursion of Accumulators. 580-584
  
• Brian Fitzgibbon, Sudhakar Pamarti, Michael Peter Kennedy:
  A Spur-Free MASH DDSM With High-Order Filtered Dither. 585-589
  
• Changbing Tang, Fangyue Chen, Xiang Li:
  Perceptron Implementation of Triple-Valued Logic Operations. 590-594
  
• Wei Ma, Mingyu Wang, Shuxi Liu, Shan Li, Peng Yu:
  Stabilizing the Average-Current-Mode-Controlled Boost PFC Converter via Washout-Filter-Aided Method. 595-599
  
• Rui Guo, Linda DeBrunner:
  Two High-Performance Adaptive Filter Implementation Schemes Using Distributed Arithmetic. 600-604
  
• Napapatch Piyachaiyakul, Chalie Charoenlarpnopparut:
  Nonseparable Three-Dimensional IIR Notch Filter Design Using Outer Product Expansion. 605-609
  
• Cagatay Candan:
  Digital Wideband Integrators With Matching Phase and Arbitrarily Accurate Magnitude Response. 610-614
  

Volume 58-II, Number 10, October 2011

• Bo-Yu Lin, Shen-Iuan Liu:
  A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS. 617-621
  
• Nawreen Khan, Masum Hossain, K. L. Eddie Law:
  A Low Power Frequency Synthesizer for 60-GHz Wireless Personal Area Networks. 622-626
  
• Yushi Zhou, Fei Yuan:
  A Study of the Lock Range of Injection-Locked CMOS Active-Inductor Oscillators Using a Linear Control System Approach. 627-631
  
• Seong-Young Seo, Jung-Hoon Chun, Young-Hyun Jun, Seok Kim, Kee-Won Kwon:
  A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity. 632-636
  
• Wei-Hao Sung, Jui-Yuan Yu, Chen-Yi Lee:
  A Robust Frequency Tracking Loop for Energy-Efficient Crystalless WBAN Systems. 637-641
  
• Jonas Fritzin, Ylva Jung, Per Niklas Landin, Peter Handel, Martin Enqvist, Atila Alvandpour:
  Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS. 642-646
  
• Giorgio Leuzzi, Vincenzo Stornelli, Stefano Del Re:
  A Tuneable Active Inductor With High Dynamic Range for Band-Pass Filter Applications. 647-651
  
• Martin Clara, Nicola Da Dalt:
  Jitter Noise of Sampled Multitone Signals. 652-656
  
• Mario Garrido, Jesús Grajal, Oscar Gustafsson:
  Optimum Circuits for Bit Reversal. 657-661
  
• Mario Garrido, Oscar Gustafsson, Jesús Grajal:
  Accurate Rotations Based on Coefficient Scaling. 662-666
  
• Davide De Caro, Nicola Petra, Antonio G. M. Strollo:
  Efficient Logarithmic Converters for Digital Signal Processing Applications. 667-671
  
• Chung-Hsun Huang, Tzung-Lin Wu, Yi-Ming Wang:
  Adaptive Pseudo Dual Keeper for Wide Fan-In Dynamic Circuits. 672-676
  
• Takashi Matsubara, Hiroyuki Torikai, Tetsuya Hishiki:
  A Generalized Rotate-and-Fire Digital Spiking Neuron Model and Its On-FPGA Learning. 677-681
  
• Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee:
  A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices. 682-686
  
• Hyung-Joon Chi, Young-Ho Choi, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park, Jong-Jin Lim, Pil-Sung Kang, Bu-Yeol Lee, Jin-Cheol Hong, Hee-Sub Lee:
  A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL. 687-691
  
• Tian-Bo Deng:
  Minimax Design of Low-Complexity Even-Order Variable Fractional-Delay Filters Using Second-Order Cone Programming. 692-696
  
• Kian Haghdad, Mohab Anis:
  Power Supply Pads Assignment for Maximum Timing Yield. 697-701
  
• Xiaoming Chen, Wei Wu, Yu Wang, Hao Yu, Huazhong Yang:
  An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation. 702-706
  

Volume 58-II, Number 11, 2011

• Chengwu Tao, Ayman A. Fayed:
  A Buck Converter With Reduced Output Spurs Using Asynchronous Frequency Hopping. 709-713
  
• Kaveh Hosseini, Brian Fitzgibbon, Michael Peter Kennedy:
  Observations Concerning the Generation of Spurious Tones in Digital Delta-Sigma Modulators Followed by a Memoryless Nonlinearity. 714-718
  
• Xiaojun Bi, Yongxin Guo, James Brinkhoff, Lin Jia, Lei Wang, Yong-Zhong Xiong, Mook Seng Leong, Fujiang Lin:
  A 60-GHz 1-V Supply Band-Tunable Power Amplifier in 65-nm CMOS. 719-723
  
• Ippei Akita, Tetsuro Itakura, Kei Shiraishi:
  Current-Steering Digital-to-Analog Converter With a High-PSRR Current Switch. 724-728
  
• Keping Wang, Zhigong Wang, XueMei Lei, Xiang Cao, Peng Han, Geliang Yang, Kaixue Ma, Kiat Seng Yeo:
  A Low-Loss Image-Reject Mixer Using Source Follower Isolation Method for DRM/DAB Tuner Applications. 729-733
  
• A. K. Gupta, K. Nagaraj, T. R. Viswanathan:
  A Two-Stage ADC Architecture With VCO-Based Second Stage. 734-738
  
• Selçuk Köse, Eby G. Friedman:
  Effective Resistance of a Two Layer Mesh. 739-743
  
• Skyler Weaver, Benjamin P. Hershberg, Nima Maghari, Un-Ku Moon:
  Domino-Logic-Based ADC for Digital Synthesis. 744-747
  
• Pascal Witte, John G. Kauffman, Joachim Becker, Maurits Ortmanns:
  A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs. 748-752
  
• Guoliang Wei, Zidong Wang, Bo Shen, Maozhen Li:
  Probability-Dependent Gain-Scheduled Filtering for Stochastic Systems With Missing Measurements. 753-757
  
• Dali Chen, YangQuan Chen, Dingyu Xue:
  Digital Fractional Order Savitzky-Golay Differentiator. 758-762
  
• Kwang-Hoon Kim, Young-Seok Choi, Seong-Eun Kim, Woo-Jin Song:
  An Affine Projection Algorithm With Periodically Evolved Update Interval. 763-767
  
• Arsenia Chorti, Mike Brookes:
  On the Effect of Voigt Profile Oscillators on OFDM Systems. 768-772
  
• Ali Montazeri, Allen Webb, Kamran Kiasaleh:
  Low-Power Spectral-Line Clock Recovery Algorithm for SDR Applications. 773-777
  
• Huy-Binh Le, Xuan-Dien Do, Sang-Gug Lee, Seung-Tak Ryu:
  A Long Reset-Time Power-On Reset Circuit With Brown-Out Detection Capability. 778-782
  

Volume 58-II, Number 12, December 2011

• Gabriel A. Rincón-Mora:
  Introduction to the Special Section on Energy-Harvesting/Scavenging Circuits and Systems. 785-786
  
• Rajiv Damodaran Prabha, Dongwon Kwon, Orlando Lazaro, Karl D. Peterson, Gabriel A. Rincón-Mora:
  Increasing Electrical Damping in Energy-Harnessing Transducers. 787-791
  
• Paul D. Mitcheson, Tzern T. Toh, Kwok H. Wong, Steve G. Burrow, Andrew S. Holmes:
  Tuning the Resonant Frequency and Damping of an Electromagnetic Energy Harvester Using Power Electronics. 792-796
  
• Antônio Carlos M. de Queiroz, Marcelo Domingues:
  The Doubler of Electricity Used as Battery Charger. 797-801
  
• Jungmoon Kim, Jihwan Kim, Chulwoo Kim:
  A Regulated Charge Pump With a Low-Power Integrated Optimum Power Point Tracking Algorithm for Indoor Solar Energy Harvesting. 802-806
  
• Mina Danesh, John R. Long:
  Photovoltaic Antennas for Autonomous Wireless Systems. 807-811
  
• Hongcheng Xu, Maurits Ortmanns:
  A Temperature and Process Compensated Ultralow-Voltage Rectifier in Standard Threshold CMOS for Energy-Harvesting Applications. 812-816
  
• Chin-Lung Yang, Yu-Lin Yang, Chun-Chih Lo:
  Subnanosecond Pulse Generators for Impulsive Wireless Power Transmission and Reception. 817-821
  
• Erez Falkenstein, Daniel Costinett, Regan Zane, Zoya Popovic:
  Far-Field RF-Powered Variable Duty Cycle Wireless Sensor Platform. 822-826
  
• Chao Shi, Brian Miller, Kartikeya Mayaram, Terri S. Fiez:
  A Multiple-Input Boost Converter for Low-Power Energy Harvesting. 827-831
  
• Yi-Chun Shih, Brian P. Otis:
  An Inductorless DC-DC Converter for Energy Harvesting With a 1.2-$ \mu\hbox{W}$ Bandgap-Referenced Output Controller. 832-836
  
• Jorge Pernillo, Michael P. Flynn:
  A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS. 837-841
  
• Gui Liu, Roc Berenguer, Yang Xu:
  A MM-Wave Configurable VCO Using MCPW-Based Tunable Inductor in 65-nm CMOS. 842-846
  
• Xuan Zhang, Ishita Mukhopadhyay, Rajeev K. Dokania, Alyssa B. Apsel:
  A 46-$\mu\hbox{W}$ Self-Calibrated Gigahertz VCO for Low-Power Radios. 847-851
  
• Alireza Kheirkhahi, Payam Naghshtabrizi, Lawrence E. Larson:
  Stability Analysis of RF Power Amplifier Envelope Feedback. 852-856
  
• Bobae Kim, Cholho Kwak, Jongsoo Lee:
  A Dual-Mode Power Amplifier With On-Chip Switch Bias Control Circuits for LTE Handsets. 857-861
  
• Manel Ben-Romdhane, Chiheb Rebai, Adel Ghazel, Patricia Desgreys, Patrick Loumeau:
  Nonuniformly Controlled Analog-to-Digital Converter for SDR Multistandard Radio Receiver. 862-866
  
• Chan-Hsiang Weng, Chen-Chien Lin, Yu-Cheng Chang, Tsung-Hsien Lin:
  A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation. 867-871
  
• Nan Sun, Peiyan Cao:
  Low-Complexity High-Order Vector-Based Mismatch Shaping in Multibit $\Delta\Sigma$ ADCs. 872-876
  
• Athanasios Stefanou, Georges G. E. Gielen:
  A Volterra Series Nonlinear Model of the Sampling Distortion in Flash ADCs Due to Substrate Noise Coupling. 877-881
  
• S. Balasubramanian, Gregory L. Creech, J. Wilson, S. M. Yoder, Jamin J. McCue, Marian Verhelst, Waleed Khalil:
  Systematic Analysis of Interleaved Digital-to-Analog Converters. 882-886
  
• Hyunsik Kim, Jinyong Jeon, Sungwoo Lee, Junhyeok Yang, Seung-Tak Ryu, Gyu-Hyeong Cho:
  A Compact-Sized 9-Bit Switched-Current DAC for AMOLED Mobile Display Drivers. 887-891
  
• César Sánchez-Perez, Jesus de Mingo, Paloma Garcia Ducar, Pedro Luis Carro, Antonio Valdovinos:
  Dynamic Load Modulation With a Reconfigurable Matching Network for Efficiency Improvement Under Antenna Mismatch. 892-896
  
• Chang-Lin Hsieh, Shen-Iuan Liu:
  Decision Feedback Equalizers Using the Back-Gate Feedback Technique. 897-901
  
• Hitesh Shrimali, Shouri Chatterjee:
  Distortion Analysis of a Three-Terminal MOS-Based Discrete-Time Parametric Amplifier. 902-905
  
• Kiarash Gharibdoust, Mehrdad Sharif Bakhtiar:
  A Method for Noise Reduction in Active-$RC$ Circuits. 906-910
  
• Alex S. Weddell, Geoff V. Merrett, Tom J. Kazmierski, Bashir M. Al-Hashimi:
  Accurate Supercapacitor Modeling for Energy Harvesting Wireless Sensor Nodes. 911-915
  
• Ruimin Huang, Chip-Hong Chang, Mathias Faust, Niklas Lotze, Yiannos Manoli:
  Sign-Extension Avoidance and Word-Length Optimization by Positive-Offset Representation for FIR Filter Design. 916-920
  
• Jun-Yong Song, Oh-Kyong Kwon:
  Low-Power 10-Gb/s Transmitter for High-Speed Graphic DRAMs Using 0.18- $\mu\hbox{m}$ CMOS Technology. 921-925
  
• Goran Molnar, Mladen Vucic:
  Closed-Form Design of CIC Compensators Based on Maximally Flat Error Criterion. 926-930
  
• Chang-Chun Hua, Xian Yang, Jing Yan, Xin-Ping Guan:
  New Exponential Stability Criteria for Neural Networks With Time-Varying Delay. 931-935
  
• Chengtao Wen, Xiaoyan Ma:
  A Canonical Piecewise-Linear Representation Theorem: Geometrical Structures Determine Representation Capability. 936-940
  

Last update Fri May 24 20:51:54 2013 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page