Volume 14, Number 1, January 2009
- Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith:
SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications.
- Andreas Hansson, Kees Goossens, Marco Bekooij, Jos Huisken:
CoMPSoC: A template for composable and predictable multi-processor system on chips.
- Stefan Valentin Gheorghita, Martin Palkovic, Juan Hamers, Arnout Vandecappelle, Stelios Mamagkakis, Twan Basten, Lieven Eeckhout, Henk Corporaal, Francky Catthoor, Frederik Vandeputte, Koen De Bosschere:
System-scenario-based design of dynamic embedded systems.
- Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty:
SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects.
- Zhong-Yi Jin, Curt Schurgers, Rajesh K. Gupta:
A gateway node with duty-cycled radio and processing subsystems for wireless sensor networks.
- Chin-Hsien Wu:
An energy-efficient I/O request mechanism for multi-bank flash-memory storage systems.
- Swapna R. Dontharaju, Shen Chih Tung, James T. Cain, Leonid Mats, Marlin H. Mickle, Alex K. Jones:
A design automation and power estimation flow for RFID systems.
- Ali Dasdan:
Provably efficient algorithms for resolving temporal and spatial difference constraint violations.
- Arnab Sinha, Pallab Dasgupta, Bhaskar Pal, Sayantan Das, Prasenjit Basu, P. P. Chakrabarti:
Design intent coverage revisited.
- Zijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivancic:
Model checking sequential software programs via mixed symbolic analysis.
- Gayatri Mehta, Justin Stander, Mustafa Baz, Brady Hunsaker, Alex K. Jones:
Interconnect customization for a hardware fabric.
- Chiu-Wing Sham, Evangeline F. Y. Young, Jingwei Lu:
Congestion prediction in early stages of physical design.
- Yi Zhu, Yuanfang Hu, Michael Bedford Taylor, Chung-Kuan Cheng:
Energy and switch area optimizations for FPGA global routing architectures.
- Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh:
Opposite-phase register switching for peak current minimization.
- Yen-Chun Lin, Li-Ling Hung:
Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2.
- Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang:
Lens aberration aware placement for timing yield.
- Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng:
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications.
- Pedro Reviriego, Juan Antonio Maestro:
Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS.
Volume 14, Number 2, March 2009
- Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran:
Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis.
- Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi:
System-level PVT variation-aware power exploration of on-chip communication architectures.
- Rajdeep Mukhopadhyay, S. K. Panda, Pallab Dasgupta, John Gough:
Instrumenting AMS assertion verification on commercial platforms.
- Martin Palkovic, Francky Catthoor, Henk Corporaal:
Trade-offs in loop transformations.
- Franco Fummi, Mirko Loghi, Massimo Poncino, Graziano Pravadelli:
A cosimulation methodology for HW/SW validation and performance estimation.
- Hiroaki Inoue, Tsuyoshi Abe, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro:
Dynamic security domain scaling on embedded symmetric multiprocessors.
- Meikang Qiu, Edwin Hsing-Mean Sha:
Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems.
- Xiangrong Zhou, Chenjie Yu, Peter Petrov:
Temperature-aware register reallocation for register file power-density minimization.
- Yu-Ru Hong, Juinn-Dar Huang:
Reducing fault dictionary size for million-gate large circuits.
- Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
Efficient partial scan cell gating for low-power scan-based testing.
- Daler N. Rakhmatov:
Battery voltage modeling for portable systems.
- Yokesh Kumar, Prosenjit Gupta:
External memory layout vs. schematic.
- Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang:
Skew-aware polarity assignment in clock tree.
- Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan:
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability.
- Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas:
FPGA-based hardware acceleration for Boolean satisfiability.
Volume 14, Number 3, May 2009
- Avinash Malik, Zoran A. Salcic, Partha S. Roop:
SystemJ compilation using the tandem virtual machine approach.
- Jason Cong, Yiping Fan, Junjuan Xu:
Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture.
- Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor:
Playing the trade-off game: Architecture exploration using Coffeee.
- Dipankar Das, P. P. Chakrabarti, Rajeev Kumar:
Scenario-based timing verification of multiprocessor embedded applications.
- Philippe Grosse, Yves Durand, Paul Feautrier:
Methods for power optimization in SOC-based data flow systems.
- Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung:
Word-length selection for power minimization via nonlinear optimization.
- Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira:
Generating realistic stimuli for accurate power grid analysis.
- Hao Yu, Joanna Ho, Lei He:
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity.
- Bo Liu, Francisco V. Fernández, Georges G. E. Gielen, R. Castro-López, Elisenda Roca:
A memetic approach to the automatic design of high-performance analog integrated circuits.
- Madhu Mutyam:
Selective shielding technique to eliminate crosstalk transitions.
- Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner:
Custom topology rotary clock router with tree subnetworks.
- Chih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Szu-Chi Wang:
High-performance obstacle-avoiding rectilinear steiner tree construction.
- Tan Yan, Martin D. F. Wong:
Theories and algorithms on single-detour routing for untangling twisted bus.
Volume 14, Number 4, August 2009
- Sivaram Gopalakrishnan, Priyank Kalla:
2009 ACM TODAES best paper award: Optimization of polynomial datapaths using finite ring algebra.
- Peter Bertels, Wim Heirman, Erik H. D'Hollander, Dirk Stroobandt:
Efficient memory management for hardware accelerated Java Virtual Machines.
- Miad Faezipour, Mehrdad Nourani, Rina Panigrahy:
A hardware platform for efficient worm outbreak detection.
- ByungHyun Lee, Ki-Seok Chung, Bontae Koo, Nak-Woong Eum, Taewhan Kim:
Thermal sensor allocation and placement for reconfigurable systems.
- Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
T-trees: A tree-based representation for temporal and three-dimensional floorplanning.
- Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin:
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.
- Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma:
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques.
- Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam:
Variation-aware multimetric optimization during gate sizing.
- Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Power-delay optimization in VLSI microprocessors by wire spacing.
- Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian:
SUPERB: Simulator utilizing parallel evaluation of resistive bridges.
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