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ORCIDACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 16
Volume 16, Number 1, November 2010
- Naehyuck Chang, Jörg Henkel:
Guest Editorial: Current Trends in Low-Power Design. 1:1-1:8 - David Bol, Denis Flandre
, Jean-Didier Legat:
Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels. 2:1-2:26 - Andrea Calimera, Enrico Macii, Massimo Poncino:
NBTI-Aware Clustered Power Gating. 3:1-3:25 - Jason Cong, Bin Liu, Rupak Majumdar, Zhiru Zhang:
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis. 4:1-4:29 - Thorlindur Thorolfsson, Samson Melamed, W. Rhett Davis, Paul D. Franzon:
Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration. 5:1-5:25 - Gaurav Dhiman, Giacomo Marchetti, Tajana Rosing:
vGreen: A System for Energy-Efficient Management of Virtual Machines. 6:1-6:27 - Jinsik Kim, Pai H. Chou:
Energy-Efficient Progressive Remote Update for Flash-Based Firmware of Networked Embedded Systems. 7:1-7:26 - Chenjie Yu, Peter Petrov:
Energy- and Performance-Efficient Communication Framework for Embedded MPSoCs through Application-Driven Release Consistency. 8:1-8:39 - Nikhil Jayakumar, Sunil P. Khatri:
A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty. 9:1-9:20 - Yu-Ze Wu, Mango Chia-Tso Chao:
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes. 10:1-10:29 - Montek Singh, Steven M. Nowick:
ACM Journal on Emerging Technologies in Computing Systems. 11:1
Volume 16, Number 2, March 2011
- Massoud Pedram:
Call for papers: Verification issue and challenges with multicore systems. 12:1 - Anna Bernasconi, Valentina Ciriani:
Dimension-reducible Boolean functions based on affine spaces. 13:1-13:21 - Yi Wang, Hui Liu, Duo Liu, Zhiwei Qin, Zili Shao, Edwin Hsing-Mean Sha:
Overhead-aware energy optimization for real-time streaming applications on multiprocessor System-on-Chip. 14:1-14:32 - Jason Cong, Wei Jiang, Bin Liu, Yi Zou:
Automatic memory partitioning and scheduling for throughput and power optimization. 15:1-15:25 - Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li:
MicroFix: Using timing interpolation and delay sensors for power reduction. 16:1-16:21 - Irith Pomeranz, Sudhakar M. Reddy:
Reducing the switching activity of test sequences under transparent-scan. 17:1-17:21 - Stephen Cauley, Venkataramanan Balakrishnan, Y. Charlie Hu, Cheng-Kok Koh:
A parallel branch-and-cut approach for detailed placement. 18:1-18:19 - Yih-Lang Li, Yu-Ning Chang, Wen-Nai Cheng:
A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment. 19:1-19:25 - Yu Liu, Kaijie Wu, Ramesh Karri:
Scan-based attacks on linear feedback shift register based stream ciphers. 20:1-20:15
Volume 16, Number 3, June 2011
- Kurt Keutzer, Peng Li, Li Shang, Hai Zhou:
A Special Section on Multicore Parallel CAD: Algorithm Design and Programming. 21:1-21:2 - Adrian Ludwin, Vaughn Betz:
Efficient and Deterministic Parallel Placement for FPGAs. 22:1-22:23 - Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala:
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm. 23:1-23:21 - Yifang Liu, Jiang Hu:
GPU-Based Parallelization for Fast Circuit Optimization. 24:1-24:14 - Chia-Jui Hsu, José Luis Pino, Shuvra S. Bhattacharyya:
Multithreaded Simulation for Synchronous Dataflow Graphs. 25:1-25:23 - Xiongfei Liao, Thambipillai Srikanthan:
Accelerating UNISIM-Based Cycle-Level Microarchitectural Simulations on Multicore Platforms. 26:1-26:25 - Antonio García Dopico, Antonio Pérez, Santiago Rodríguez, Maria Isabel García:
A New Algorithm for VHDL Parallel Simulation. 27:1-27:31 - Zhiyu Zeng, Zhuo Feng, Peng Li, Vivek Sarin:
Locality-Driven Parallel Static Analysis for Power Delivery Networks. 28:1-28:17 - Yuhao Zhu, Bo D. Wang, Yangdong Deng:
Massively Parallel Logic Simulation with GPUs. 29:1-29:20 - Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco:
Gate-Level Simulation with GPU Computing. 30:1-30:26 - Rajdeep Bondade, Dongsheng Ma:
Hardware-Software Codesign of an Embedded Multiple-Supply Power Management Unit for Multicore SoCs Using an Adaptive Global/Local Power Allocation and Processing Scheme. 31:1-31:27 - Greg Stitt, Frank Vahid:
Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators. 32:1-32:21 - Antara Ain, Debjit Pal, Pallab Dasgupta, Siddhartha Mukhopadhyay, Rajdeep Mukhopadhyay, John Gough:
Chassis: A Platform for Verifying PMU Integration Using Autogenerated Behavioral Models. 33:1-33:30 - Yue Yu, Shangping Ren, Xiaobo Sharon Hu:
A Metric for Quantifying Similarity between Timing Constraint Sets in Real-Time Systems. 34:1-34:33 - Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Tiempo Sas, Gilles Sicard:
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications. 35:1-35:17
Volume 16, Number 4, October 2011
- Meikang Qiu, Edwin Hsing-Mean Sha:
2011 ACM TODAES best paper award. 36:1 - Alper Sen:
Concurrency-oriented verification and coverage of system-level designs. 37:1-37:25 - Laurent Fournier, Avi Ziv, Ekaterina Kutsy, Ofer Strichman:
A probabilistic analysis of coverage methods. 38:1-38:20 - Wei-Tsun Sun, Zoran Salcic:
GALS-Designer: A design framework for GALS software systems. 39:1-39:24 - Kartikey Mittal, Arpit Joshi, Madhu Mutyam:
Timing variation-aware scheduling and resource binding in high-level synthesis. 40:1-40:19 - Xiaofang (Maggie) Wang, Pallav Gupta:
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs. 41:1-41:29 - Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunheung Paek:
Memory access optimization in compilation for coarse-grained reconfigurable architectures. 42:1-42:27 - Karel Bruneel, Wim Heirman, Dirk Stroobandt:
Dynamic data folding with parameterizable FPGA configurations. 43:1-43:29 - Wei Dong, Peng Li:
Parallel circuit simulation with adaptively controlled projective integration. 44:1-44:24 - Juan Antonio Maestro, Pedro Reviriego, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong:
Mitigating the effects of large multiple cell upsets (MCUs) in memories. 45:1-45:10 - Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim:
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation. 46:1-46:25 - Jin-Tai Yan:
IO connection assignment and RDL routing for flip-chip designs. 47:1-47:20 - Tak-Yung Kim, Taewhan Kim:
Clock Tree synthesis for TSV-based 3D IC designs. 48:1-48:21 - Jianchao Lu, Baris Taskin:
Clock buffer polarity assignment with skew tuning. 49:1-49:22 - Shaoxi Wang, Xinzhang Jia, Arthur B. Yeh, Lihong Zhang:
Analog layout retargeting using geometric programming. 50:1-50:11 - Filipa Duarte, Jos Hulzink, Jun Zhou, Jan Stuijt, Jos Huisken, Harmke de Groot:
A 36μW heartbeat-detection processor for a wireless sensor node. 51:1-51:19
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