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ORCIDThe Journal of VLSI Signal Processing, Volume 24
Volume 24, Number 1, February 2000
- Elias S. Manolakos, Wayne P. Burleson:
Guest Editor's Introduction. 5-6 - Paul D. Fiore:
Efficient Wordlength Reduction Techniques for DSP Applications. 9-18 - Shiro Kobayashi, Gerhard P. Fettweis:
A Hierarchical Block-Floating-Point Arithmetic. 19-30 - Richard P. Kleihorst, René J. van der Vleuten:
DCT-Domain Embedded Memory Compression for Hybrid Video Coders. 31-41 - Sangjin Hong, Wayne E. Stark:
Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications. 43-57 - Sydney Reader, Won Namgoong, Teresa H. Meng:
Partitioning Analog and Digital Processing in Mixed-Signal Systems. 59-65 - Gaye Lightbody
, Richard L. Walke, Roger F. Woods, John V. McCanny:
Linear QR Architecture for a Single Chip Adaptive Beamformer. 67-81 - Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya:
Multidimensional Exploration of Software Implementations for DSP Algorithms. 83-98 - Andrew Stone, Elias S. Manolakos:
DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures. 99-120
Volume 24, Numbers 2-3, March 2000
- Jeffrey Arnold, Wayne Luk, Ken Pocek:
Guest Editors' Introduction. 127 - Herman Schmit, Srihari Cadambi, Matthew Moe, Seth Copen Goldstein:
Pipeline Reconfigurable FPGAs. 129-146 - Ming-Hau Lee, Hartej Singh, Guangming Lu, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves:
Design and Implementation of the MorphoSys Reconfigurable Computing Processor. 147-164 - Maya B. Gokhale, Janice M. Stone, Edson Gomersall:
Co-Synthesis to a Hybrid RISC/FPGA Architecture. 165-180 - Meenakshi Kaul, Ranga Vemuri:
Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems. 181-209 - Oskar Mencer, Luc Séméria, Martin Morf, Jean-Marc Delosme:
Application of Reconfigurable CORDIC Architectures. 211-221 - Panagiotis Stogiannos, Apostolos Dollas, Vassilios Digalakis:
A Configurable Logic Based Architecture for Real-Time Continuous Speech Recognition Using Hidden Markov Models. 223-240 - Hugo de Garis, Michael Korkin:
The CAM-Brain Machine (CBM): Real Time Evolution and Update of a 75 Million Neuron FPGA-Based Artificial Brain. 241-262
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