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ORCIDJournal of Signal Processing Systems, Volume 71
Volume 71, Number 1, April 2013
- Alexandre Borghi, Jérôme Darbon, Sylvain Peyronnet, Tony F. Chan
, Stanley J. Osher:
A Simple Compressive Sensing Algorithm for Parallel Many-Core Architectures. 1-20 - Shiyan Wang, Huimin Yu, Roland Hu:
3D Video Based Segmentation and Motion Estimation with Active Surface Evolution. 21-34 - Jani Boutellier, Mickaël Raulet, Olli Silvén:
Automatic Hierarchical Discovery of Quasi-Static Schedules of RVC-CAL Dataflow Programs. 35-40 - Milad Ghantous, Magdy A. Bayoumi:
MIRF: A Multimodal Image Registration and Fusion Module Based on DT-CWT. 41-55 - Marek Wójcikowski, Robert Zaglewski, Bogdan Pankiewicz, Miron Klosowski, Stanislaw Szczepanski:
Hardware-Software Implementation of a Sensor Network for City Traffic Monitoring Using the FPGA- and ASIC-Based Sensor Nodes. 57-73 - Hyunok Oh:
Port Based Actor Model with Kahn Process Network Model and Decidable Dataflow Model. 75-88
Volume 71, Number 2, May 2013
- Rafael Ramos-Lara, Mariano López-García, Enrique F. Cantó-Navarro, Luis Puente-Rodriguez:
Real-Time Speaker Verification System Implemented on Reconfigurable Hardware. 89-103 - Pedro Echeverría, Marisa López-Vallejo:
High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator. 105-109 - Mohammad Reza Hosseiny Fatemi, Hasan F. Ates, Rosli Salleh:
Analysis and Design of Low-Cost Bit-Serial Architectures for Motion Estimation in H.264/AVC. 111-121 - Ishmael Sameen, Yoong Choon Chang, Mow Song Ng, Bok-Min Goi, Chee-Pun Ooi:
A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform. 123-142 - Jingtong Hu, Chun Jason Xue, Meikang Qiu, Wei-Che Tseng, Edwin Hsing-Mean Sha:
Algorithms to Minimize Data Transfer for Code Update on Wireless Sensor Network. 143-157 - Jaehyun Baek, Myung Hoon Sunwoo:
New Cost-Effective Simplified Euclid's Algorithm for Reed-Solomon Decoders. 159-168
Volume 71, Number 3, June 2013
- Jarmo Takala, Warren J. Gross, Wonyong Sung:
Guest Editors' Introduction to Special Issue on Advances in DSP System Design. 169-171 - Wei-Chih Lai, Ching-Te Chiu:
Data Center Switch for Load Balanced Fat-Trees. 173-187 - Dong-hwan Lee, Wonyong Sung:
Least Squares Based Coupling Cancelation for MLC NAND Flash Memory with a Small Number of Voltage Sensing Operations. 189-200 - Mohammad M. Mansour:
A Fast Recursive Algorithm and Architecture for Pruned Bit-reversal Interleavers. 201-219 - Ricardo M. Sanchez, Paul A. Rodríguez:
Highly Parallelable Bidimensional Median Filter for Modern Parallel Programming Models. 221-235 - Yun Pan, Ning Zheng, Qinglin Tian, Xiaolang Yan, Ruohong Huan:
Hierarchical Resampling Algorithm and Architecture for Distributed Particle Filters. 237-246 - Chi Ching Chi, Mauricio Alvarez-Mesa, Jan Lucas, Ben H. H. Juurlink, Thomas Schierl:
Parallel HEVC Decoding on Multi- and Many-core Architectures - A Power and Performance Analysis. 247-260 - Jiayi Du, Yan Wang, Qingfeng Zhuge, Jingtong Hu, Edwin Hsing-Mean Sha:
Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory. 261-273 - Lai-Huei Wang, Chung-Ching Shen, Shenpei Wu, Shuvra S. Bhattacharyya:
Parameterized Scheduling of Topological Patterns in Signal Processing Dataflow Graphs. 275-286 - Helena Leppäkoski, Jussi Collin, Jarmo Takala:
Pedestrian Navigation Based on Inertial Sensors, Indoor Map, and WLAN Signals. 287-296 - Qiuling Zhu, Christian R. Berger, Eric L. Turner, Larry T. Pileggi, Franz Franchetti:
Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation. 297-312
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