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ORCIDBibTeX records: Ran Ginosar
@article{DBLP:journals/tpds/YavitsKG22,
author = {Leonid Yavits and
Roman Kaplan and
Ran Ginosar},
title = {{GIRAF:} General Purpose In-Storage Resistive Associative Framework},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {33},
number = {2},
pages = {276--287},
year = {2022},
url = {https://doi.org/10.1109/TPDS.2021.3065448},
doi = {10.1109/TPDS.2021.3065448},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tpds/YavitsKG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jce/AzrielSAGMP21,
author = {Leonid Azriel and
Julian Speith and
Nils Albartus and
Ran Ginosar and
Avi Mendelson and
Christof Paar},
title = {A survey of algorithmic methods in {IC} reverse engineering},
journal = {J. Cryptogr. Eng.},
volume = {11},
number = {3},
pages = {299--315},
year = {2021},
url = {https://doi.org/10.1007/s13389-021-00268-5},
doi = {10.1007/S13389-021-00268-5},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jce/AzrielSAGMP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/AzrielSAGMP21,
author = {Leonid Azriel and
Julian Speith and
Nils Albartus and
Ran Ginosar and
Avi Mendelson and
Christof Paar},
title = {A survey of algorithmic methods in {IC} reverse engineering},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {1278},
year = {2021},
url = {https://eprint.iacr.org/2021/1278},
timestamp = {Mon, 25 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iacr/AzrielSAGMP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/YavitsOMFEGM20,
author = {Leonid Yavits and
Lois Orosa and
Suyash Mahar and
Jo{\~{a}}o Dinis Ferreira and
Mattan Erez and
Ran Ginosar and
Onur Mutlu},
title = {WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive
Memories using Programmable Address Decoders},
booktitle = {38th {IEEE} International Conference on Computer Design, {ICCD} 2020,
Hartford, CT, USA, October 18-21, 2020},
pages = {187--196},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICCD50377.2020.00044},
doi = {10.1109/ICCD50377.2020.00044},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/YavitsOMFEGM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/systor/KaplanYG20,
author = {Roman Kaplan and
Leonid Yavits and
Ran Ginosar},
editor = {Bianca Schroeder and
Danny Harnik},
title = {BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale
Genomic Data},
booktitle = {{SYSTOR} 2020: The 13th {ACM} International Systems and Storage Conference,
Haifa, Israel, October 13-15, 2020},
pages = {36--48},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3383669.3398279},
doi = {10.1145/3383669.3398279},
timestamp = {Mon, 15 Jun 2020 11:47:37 +0200},
biburl = {https://dblp.org/rec/conf/systor/KaplanYG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2010-02825,
author = {Leonid Yavits and
Lois Orosa and
Suyash Mahar and
Jo{\~{a}}o Dinis Ferreira and
Mattan Erez and
Ran Ginosar and
Onur Mutlu},
title = {WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive
Memories using Programmable Address Decoders},
journal = {CoRR},
volume = {abs/2010.02825},
year = {2020},
url = {https://arxiv.org/abs/2010.02825},
eprinttype = {arXiv},
eprint = {2010.02825},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2010-02825.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/KaplanYG19,
author = {Roman Kaplan and
Leonid Yavits and
Ran Ginosar},
title = {{RASSA:} Resistive Prealignment Accelerator for Approximate {DNA}
Long Read Mapping},
journal = {{IEEE} Micro},
volume = {39},
number = {4},
pages = {44--54},
year = {2019},
url = {https://doi.org/10.1109/MM.2018.2890253},
doi = {10.1109/MM.2018.2890253},
timestamp = {Wed, 31 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/KaplanYG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/RamadanWGK19,
author = {Misbah Ramadan and
Nicol{\'{a}}s Wainstein and
Ran Ginosar and
Shahar Kvatinsky},
title = {Adaptive programming in multi-level cell ReRAM},
journal = {Microelectron. J.},
volume = {90},
pages = {169--180},
year = {2019},
url = {https://doi.org/10.1016/j.mejo.2019.06.004},
doi = {10.1016/J.MEJO.2019.06.004},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/RamadanWGK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/KaplanYG19,
author = {Roman Kaplan and
Leonid Yavits and
Ran Ginosar},
title = {{POSTER:} BioSEAL: In-Memory Biological Sequence Alignment Accelerator
for Large-Scale Genomic Data},
booktitle = {28th International Conference on Parallel Architectures and Compilation
Techniques, {PACT} 2019, Seattle, WA, USA, September 23-26, 2019},
pages = {459--460},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/PACT.2019.00044},
doi = {10.1109/PACT.2019.00044},
timestamp = {Wed, 13 Nov 2019 18:02:12 +0100},
biburl = {https://dblp.org/rec/conf/IEEEpact/KaplanYG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/YavitsKG19,
author = {Leonid Yavits and
Roman Kaplan and
Ran Ginosar},
title = {{POSTER:} {GIRAF:} General Purpose In-Storage Resistive Associative
Framework},
booktitle = {28th International Conference on Parallel Architectures and Compilation
Techniques, {PACT} 2019, Seattle, WA, USA, September 23-26, 2019},
pages = {477--478},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/PACT.2019.00053},
doi = {10.1109/PACT.2019.00053},
timestamp = {Wed, 13 Nov 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/IEEEpact/YavitsKG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ccs/AzrielGM19,
author = {Leonid Azriel and
Ran Ginosar and
Avi Mendelson},
editor = {Chip{-}Hong Chang and
Ulrich R{\"{u}}hrmair and
Daniel E. Holcomb and
Patrick Schaumont},
title = {SoK: An Overview of Algorithmic Methods in {IC} Reverse Engineering},
booktitle = {Proceedings of the 3rd {ACM} Workshop on Attacks and Solutions in
Hardware Security Workshop, ASHES@CCS 2019, London, UK, November 15,
2019},
pages = {65--74},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3338508.3359575},
doi = {10.1145/3338508.3359575},
timestamp = {Tue, 10 Nov 2020 16:06:16 +0100},
biburl = {https://dblp.org/rec/conf/ccs/AzrielGM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1901-04976,
author = {Leonid Yavits and
Roman Kaplan and
Ran Ginosar},
title = {{AIDA:} Associative {DNN} Inference Accelerator},
journal = {CoRR},
volume = {abs/1901.04976},
year = {2019},
url = {http://arxiv.org/abs/1901.04976},
eprinttype = {arXiv},
eprint = {1901.04976},
timestamp = {Fri, 01 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1901-04976.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1901-05959,
author = {Roman Kaplan and
Leonid Yavits and
Ran Ginosar},
title = {BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale
Genomic Data},
journal = {CoRR},
volume = {abs/1901.05959},
year = {2019},
url = {http://arxiv.org/abs/1901.05959},
eprinttype = {arXiv},
eprint = {1901.05959},
timestamp = {Fri, 01 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1901-05959.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/YavitsG18,
author = {Leonid Yavits and
Ran Ginosar},
title = {Accelerator for Sparse Machine Learning},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {17},
number = {1},
pages = {21--24},
year = {2018},
url = {https://doi.org/10.1109/LCA.2017.2714667},
doi = {10.1109/LCA.2017.2714667},
timestamp = {Sun, 15 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/YavitsG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/YavitsKG18,
author = {Leonid Yavits and
Roman Kaplan and
Ran Ginosar},
title = {Enabling Full Associativity with Memristive Address Decoder},
journal = {{IEEE} Micro},
volume = {38},
number = {5},
pages = {32--40},
year = {2018},
url = {https://doi.org/10.1109/MM.2018.053631139},
doi = {10.1109/MM.2018.053631139},
timestamp = {Fri, 12 Oct 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/YavitsKG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1805-09612,
author = {Leonid Yavits and
Roman Kaplan and
Ran Ginosar},
title = {{PRINS:} Resistive {CAM} Processing in Storage},
journal = {CoRR},
volume = {abs/1805.09612},
year = {2018},
url = {http://arxiv.org/abs/1805.09612},
eprinttype = {arXiv},
eprint = {1805.09612},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1805-09612.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1809-01127,
author = {Roman Kaplan and
Leonid Yavits and
Ran Ginosar},
title = {{RASSA:} Resistive Accelerator for Approximate Long Read {DNA} Mapping},
journal = {CoRR},
volume = {abs/1809.01127},
year = {2018},
url = {http://arxiv.org/abs/1809.01127},
eprinttype = {arXiv},
eprint = {1809.01127},
timestamp = {Fri, 05 Oct 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1809-01127.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/YavitsWG17,
author = {Leonid Yavits and
Uri C. Weiser and
Ran Ginosar},
title = {Resistive Address Decoder},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {16},
number = {2},
pages = {141--144},
year = {2017},
url = {https://doi.org/10.1109/LCA.2017.2670539},
doi = {10.1109/LCA.2017.2670539},
timestamp = {Sun, 15 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/YavitsWG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangDUNSMG17,
author = {Y. Zhang and
Rostislav (Reuven) Dobkin and
Aharon Unikovski and
Danniel Nahmanny and
Goel Samuel and
Michael Moyal and
Ran Ginosar},
title = {A 1.4{\texttimes}FO4 self-clocked asynchronous serial link in 0.18
{\(\mathrm{\mu}\)}m for intrachip communication},
journal = {Integr.},
volume = {59},
pages = {190--197},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.007},
doi = {10.1016/J.VLSI.2017.06.007},
timestamp = {Mon, 01 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangDUNSMG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/KaplanYGW17,
author = {Roman Kaplan and
Leonid Yavits and
Ran Ginosar and
Uri C. Weiser},
title = {A Resistive {CAM} Processing-in-Storage Architecture for {DNA} Sequence
Alignment},
journal = {{IEEE} Micro},
volume = {37},
number = {4},
pages = {20--28},
year = {2017},
url = {https://doi.org/10.1109/MM.2017.3211121},
doi = {10.1109/MM.2017.3211121},
timestamp = {Wed, 06 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/KaplanYGW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/superfri/KaplanYG17,
author = {Roman Kaplan and
Leonid Yavits and
Ran Ginosar},
title = {From Processing-in-Memory to Processing-in-Storage},
journal = {Supercomput. Front. Innov.},
volume = {4},
number = {3},
pages = {99--116},
year = {2017},
url = {https://doi.org/10.14529/jsfi170307},
doi = {10.14529/JSFI170307},
timestamp = {Tue, 15 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/superfri/KaplanYG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AzrielGGM17,
author = {Leonid Azriel and
Ran Ginosar and
Shay Gueron and
Avi Mendelson},
title = {Using Scan Side Channel to Detect {IP} Theft},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3268--3280},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2715188},
doi = {10.1109/TVLSI.2017.2715188},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AzrielGGM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AzrielGM17,
author = {Leonid Azriel and
Ran Ginosar and
Avi Mendelson},
editor = {Laleh Behjat and
Jie Han and
Miroslav N. Velev and
Deming Chen},
title = {Revealing On-chip Proprietary Security Functions with Scan Side Channel
Based Reverse Engineering},
booktitle = {Proceedings of the on Great Lakes Symposium on {VLSI} 2017, Banff,
AB, Canada, May 10-12, 2017},
pages = {233--238},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3060403.3060464},
doi = {10.1145/3060403.3060464},
timestamp = {Tue, 06 Nov 2018 16:59:34 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/AzrielGM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/KaplanYGW17,
author = {Roman Kaplan and
Leonid Yavits and
Ran Ginosar and
Uri C. Weiser},
title = {A Resistive {CAM} Processing-in-Storage Architecture for {DNA} Sequence
Alignment},
journal = {CoRR},
volume = {abs/1701.04723},
year = {2017},
url = {http://arxiv.org/abs/1701.04723},
eprinttype = {arXiv},
eprint = {1701.04723},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/KaplanYGW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/YavitsMWG17,
author = {Leonid Yavits and
Amir Morad and
Uri C. Weiser and
Ran Ginosar},
title = {MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures},
journal = {CoRR},
volume = {abs/1705.06923},
year = {2017},
url = {http://arxiv.org/abs/1705.06923},
eprinttype = {arXiv},
eprint = {1705.06923},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/YavitsMWG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/YavitsMG17,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {The Effect of Temperature on Amdahl Law in 3D Multicore Era},
journal = {CoRR},
volume = {abs/1705.07280},
year = {2017},
url = {http://arxiv.org/abs/1705.07280},
eprinttype = {arXiv},
eprint = {1705.07280},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/YavitsMG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/YavitsMG17a,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {Cache Hierarchy Optimization},
journal = {CoRR},
volume = {abs/1705.07281},
year = {2017},
url = {http://arxiv.org/abs/1705.07281},
eprinttype = {arXiv},
eprint = {1705.07281},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/YavitsMG17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/YavitsMG17b,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {Sparse Matrix Multiplication On An Associative Processor},
journal = {CoRR},
volume = {abs/1705.07282},
year = {2017},
url = {http://arxiv.org/abs/1705.07282},
eprinttype = {arXiv},
eprint = {1705.07282},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/YavitsMG17b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/YavitsG17,
author = {Leonid Yavits and
Ran Ginosar},
title = {Sparse Matrix Multiplication on {CAM} Based Accelerator},
journal = {CoRR},
volume = {abs/1705.09937},
year = {2017},
url = {http://arxiv.org/abs/1705.09937},
eprinttype = {arXiv},
eprint = {1705.09937},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/YavitsG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/RotemWMGWA16,
author = {Efraim Rotem and
Uri C. Weiser and
Avi Mendelson and
Ran Ginosar and
Eliezer Weissmann and
Yoni Aizik},
title = {H-EARtH: Heterogeneous Multicore Platform Energy Management},
journal = {Computer},
volume = {49},
number = {10},
pages = {47--55},
year = {2016},
url = {https://doi.org/10.1109/MC.2016.309},
doi = {10.1109/MC.2016.309},
timestamp = {Wed, 12 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/RotemWMGWA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/MoradYKG16,
author = {Amir Morad and
Leonid Yavits and
Shahar Kvatinsky and
Ran Ginosar},
title = {Resistive {GP-SIMD} Processing-In-Memory},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {12},
number = {4},
pages = {57:1--57:22},
year = {2016},
url = {https://doi.org/10.1145/2845084},
doi = {10.1145/2845084},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/MoradYKG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/YavitsMG16,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {The Effect of Temperature on Amdahl Law in 3D Multicore Era},
journal = {{IEEE} Trans. Computers},
volume = {65},
number = {6},
pages = {2010--2013},
year = {2016},
url = {https://doi.org/10.1109/TC.2015.2458865},
doi = {10.1109/TC.2015.2458865},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/YavitsMG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/AzrielGGM16,
author = {Leonid Azriel and
Ran Ginosar and
Shay Gueron and
Avi Mendelson},
title = {Using Scan Side Channel for Detecting {IP} Theft},
booktitle = {Proceedings of the Hardware and Architectural Support for Security
and Privacy 2016, HASP@ICSA 2016, Seoul, Republic of Korea, June 18,
2016},
pages = {1:1--1:8},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2948618.2948619},
doi = {10.1145/2948618.2948619},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isca/AzrielGGM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KaplanYMG16,
author = {Roman Kaplan and
Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {Deduplication in resistive content addressable memory based solid
state drive},
booktitle = {26th International Workshop on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2016, Bremen, Germany, September 21-23, 2016},
pages = {100--106},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/PATMOS.2016.7833432},
doi = {10.1109/PATMOS.2016.7833432},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KaplanYMG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/YavitsMGW16,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar and
Uri C. Weiser},
title = {Convex Optimization of Real Time SoC},
journal = {CoRR},
volume = {abs/1601.07815},
year = {2016},
url = {http://arxiv.org/abs/1601.07815},
eprinttype = {arXiv},
eprint = {1601.07815},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/YavitsMGW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/YavitsMG16,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {Effect of Data Sharing on Private Cache Design in Chip Multiprocessors},
journal = {CoRR},
volume = {abs/1602.01329},
year = {2016},
url = {http://arxiv.org/abs/1602.01329},
eprinttype = {arXiv},
eprint = {1602.01329},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/YavitsMG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/YavitsKMG15,
author = {Leonid Yavits and
Shahar Kvatinsky and
Amir Morad and
Ran Ginosar},
title = {Resistive Associative Processor},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {14},
number = {2},
pages = {148--151},
year = {2015},
url = {https://doi.org/10.1109/LCA.2014.2374597},
doi = {10.1109/LCA.2014.2374597},
timestamp = {Sun, 15 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/YavitsKMG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/RotemGMW15,
author = {Efraim Rotem and
Ran Ginosar and
Avi Mendelson and
Uri C. Weiser},
title = {Power and thermal constraints of modern system-on-a-chip computer},
journal = {Microelectron. J.},
volume = {46},
number = {12},
pages = {1225--1229},
year = {2015},
url = {https://doi.org/10.1016/j.mejo.2015.09.002},
doi = {10.1016/J.MEJO.2015.09.002},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/RotemGMW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/YavitsMG15,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {Computer Architecture with Associative Processor Replacing Last-Level
Cache and {SIMD} Accelerator},
journal = {{IEEE} Trans. Computers},
volume = {64},
number = {2},
pages = {368--381},
year = {2015},
url = {https://doi.org/10.1109/TC.2013.220},
doi = {10.1109/TC.2013.220},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/YavitsMG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/CannizzaroBCGL15,
author = {Marco Cannizzaro and
Salomon Beer and
Jordi Cortadella and
Ran Ginosar and
Luciano Lavagno},
title = {SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {62-I},
number = {9},
pages = {2238--2247},
year = {2015},
url = {https://doi.org/10.1109/TCSI.2014.2365878},
doi = {10.1109/TCSI.2014.2365878},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/CannizzaroBCGL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/YavitsMG15,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {Sparse Matrix Multiplication On An Associative Processor},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {26},
number = {11},
pages = {3175--3183},
year = {2015},
url = {https://doi.org/10.1109/TPDS.2014.2370055},
doi = {10.1109/TPDS.2014.2370055},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/YavitsMG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BeerG15,
author = {Salomon Beer and
Ran Ginosar},
title = {Eleven Ways to Boost Your Synchronizer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {6},
pages = {1040--1049},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2331331},
doi = {10.1109/TVLSI.2014.2331331},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BeerG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BeerG15a,
author = {Salomon Beer and
Ran Ginosar},
title = {A Model for Supply Voltage and Temperature Variation Effects on Synchronizer
Performance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {11},
pages = {2461--2472},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2365255},
doi = {10.1109/TVLSI.2014.2365255},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BeerG15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BeerCGCZ15,
author = {Salomon Beer and
Jerome Cox and
Ran Ginosar and
Tom Chaney and
David M. Zar},
title = {Variability in Multistage Synchronizers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {12},
pages = {2957--2969},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2387391},
doi = {10.1109/TVLSI.2014.2387391},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BeerCGCZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DiamantGS15,
author = {Ron Diamant and
Ran Ginosar and
Christos P. Sotiriou},
title = {Asynchronous sub-threshold ultra-low power processor},
booktitle = {25th International Workshop on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2015, Salvador, Brazil, September 1-4, 2015},
pages = {89--96},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/PATMOS.2015.7347592},
doi = {10.1109/PATMOS.2015.7347592},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/patmos/DiamantGS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/RotemGWM14,
author = {Efraim Rotem and
Ran Ginosar and
Uri C. Weiser and
Avi Mendelson},
title = {Energy Aware Race to Halt: {A} Down to EARtH Approach for Platform
Energy Management},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {13},
number = {1},
pages = {25--28},
year = {2014},
url = {https://doi.org/10.1109/L-CA.2012.32},
doi = {10.1109/L-CA.2012.32},
timestamp = {Sun, 15 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/RotemGWM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/MoradMYGW14,
author = {Amir Morad and
Tomer Y. Morad and
Leonid Yavits and
Ran Ginosar and
Uri C. Weiser},
title = {Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator
SoC},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {13},
number = {1},
pages = {37--40},
year = {2014},
url = {https://doi.org/10.1109/L-CA.2012.34},
doi = {10.1109/L-CA.2012.34},
timestamp = {Sun, 15 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/MoradMYGW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/YavitsMG14,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {Cache Hierarchy Optimization},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {13},
number = {2},
pages = {69--72},
year = {2014},
url = {https://doi.org/10.1109/L-CA.2013.18},
doi = {10.1109/L-CA.2013.18},
timestamp = {Sun, 15 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cal/YavitsMG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VerbitskyDGB14,
author = {Dmitry Verbitsky and
Rostislav (Reuven) Dobkin and
Ran Ginosar and
Salomon Beer},
title = {StarSync: An extendable standard-cell mesochronous synchronizer},
journal = {Integr.},
volume = {47},
number = {2},
pages = {250--260},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.09.003},
doi = {10.1016/J.VLSI.2013.09.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/VerbitskyDGB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pc/YavitsMG14,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {The effect of communication and synchronization on Amdahl's law in
multicore systems},
journal = {Parallel Comput.},
volume = {40},
number = {1},
pages = {1--16},
year = {2014},
url = {https://doi.org/10.1016/j.parco.2013.11.001},
doi = {10.1016/J.PARCO.2013.11.001},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/pc/YavitsMG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/Haj-YihiaBRYG14,
author = {Jawad Haj{-}Yihia and
Yosi Ben{-}Asher and
Efraim Rotem and
Ahmad Yasin and
Ran Ginosar},
title = {Compiler-Directed Power Management for Superscalars},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {11},
number = {4},
pages = {48:1--48:21},
year = {2014},
url = {https://doi.org/10.1145/2685393},
doi = {10.1145/2685393},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/Haj-YihiaBRYG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/MoradYG14,
author = {Amir Morad and
Leonid Yavits and
Ran Ginosar},
title = {{GP-SIMD} Processing-in-Memory},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {11},
number = {4},
pages = {53:1--53:26},
year = {2014},
url = {https://doi.org/10.1145/2686875},
doi = {10.1145/2686875},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/MoradYG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/GinosarC14,
author = {Ran Ginosar and
Karam S. Chatha},
title = {Guest Editors' Introduction - Special Issue on Network-on-Chip},
journal = {{IEEE} Trans. Computers},
volume = {63},
number = {3},
pages = {527--528},
year = {2014},
url = {https://doi.org/10.1109/TC.2014.6},
doi = {10.1109/TC.2014.6},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/GinosarC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/BeerCCGL14,
author = {Salomon Beer and
Marco Cannizzaro and
Jordi Cortadella and
Ran Ginosar and
Luciano Lavagno},
title = {Metastability in Better-Than-Worst-Case Designs},
booktitle = {20th {IEEE} International Symposium on Asynchronous Circuits and Systems,
{ASYNC} 2014, Potsdam, Germany, May 12-14, 2014},
pages = {101--102},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ASYNC.2014.21},
doi = {10.1109/ASYNC.2014.21},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/BeerCCGL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/AvronG14,
author = {Itai Avron and
Ran Ginosar},
editor = {Masoumeh Ebrahimi and
Diana Goehringer and
Masoud Daneshtalab and
Maurizio Palesi and
S{\"{o}}ren Sonntag and
Federico Angiolini},
title = {Hardware Scheduler Performance on the Plural Many-Core Architecture},
booktitle = {Proceedings of the 3rd International Workshop on Many-core Embedded
Systems (MES'2015) held on June 13, 2015 in conjunction with the 42nd
International Symposium on Computer Architecture (ISCA'2015), Portland,
OR, {USA}},
pages = {48--51},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2768177.2768184},
doi = {10.1145/2768177.2768184},
timestamp = {Fri, 09 Jul 2021 15:51:20 +0200},
biburl = {https://dblp.org/rec/conf/isca/AvronG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MoradYG14,
author = {Amir Morad and
Leonid Yavits and
Ran Ginosar},
title = {Efficient Dense and Sparse Matrix Multiplication on {GP-SIMD}},
booktitle = {24th International Workshop on Power and Timing Modeling, Optimization
and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 -
Oct. 1, 2014},
pages = {1--8},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/PATMOS.2014.6951895},
doi = {10.1109/PATMOS.2014.6951895},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MoradYG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MoradYG14a,
author = {Amir Morad and
Leonid Yavits and
Ran Ginosar},
title = {Convex optimization of resource allocation in asymmetric and heterogeneous
SoC},
booktitle = {24th International Workshop on Power and Timing Modeling, Optimization
and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 -
Oct. 1, 2014},
pages = {1--8},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/PATMOS.2014.6951864},
doi = {10.1109/PATMOS.2014.6951864},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MoradYG14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/RotemWMYG14,
author = {Efraim Rotem and
Uri C. Weiser and
Avi Mendelson and
Ahmad Yasin and
Ran Ginosar},
title = {Energy management of highly dynamic server workloads in an heterogeneous
data center},
booktitle = {24th International Workshop on Power and Timing Modeling, Optimization
and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 -
Oct. 1, 2014},
pages = {1--5},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/PATMOS.2014.6951868},
doi = {10.1109/PATMOS.2014.6951868},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/RotemWMYG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AbdelhadiGKF13,
author = {Ameer Abdelhadi and
Ran Ginosar and
Avinoam Kolodny and
Eby G. Friedman},
title = {Timing-driven variation-aware synthesis of hybrid mesh/tree clock
distribution networks},
journal = {Integr.},
volume = {46},
number = {4},
pages = {382--391},
year = {2013},
url = {https://doi.org/10.1016/j.vlsi.2012.12.001},
doi = {10.1016/J.VLSI.2012.12.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AbdelhadiGKF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/3dic/YavitsMG13,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {3D cache hierarchy optimization},
booktitle = {2013 {IEEE} International 3D Systems Integration Conference (3DIC),
San Francisco, CA, USA, October 2-4, 2013},
pages = {1--5},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/3DIC.2013.6702346},
doi = {10.1109/3DIC.2013.6702346},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/3dic/YavitsMG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/BeerGDW13,
author = {Salomon Beer and
Ran Ginosar and
Rostislav (Reuven) Dobkin and
Yoav Weizman},
title = {{MTBF} Estimation in Coherent Clock Domains},
booktitle = {19th {IEEE} International Symposium on Asynchronous Circuits and Systems,
{ASYNC} 2013, Santa Monica, CA, USA, May 19-22, 2013},
pages = {166--173},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ASYNC.2013.19},
doi = {10.1109/ASYNC.2013.19},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/BeerGDW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BeerGCCZ13,
author = {Salomon Beer and
Ran Ginosar and
Jerome Cox and
Tom Chaney and
David M. Zar},
editor = {Enrico Macii},
title = {Metastability challenges for 65nm and beyond: simulation and measurements},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {1297--1302},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.268},
doi = {10.7873/DATE.2013.268},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/BeerGCCZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NaveG13,
author = {Eyal{-}Itzhak Nave and
Ran Ginosar},
editor = {Jos{\'{e}} Luis Ayala and
Alex K. Jones and
Patrick H. Madden and
Ayse K. Coskun},
title = {{PBD:} packet buffer DVFs},
booktitle = {Great Lakes Symposium on {VLSI} 2013 (part of ECRC), GLSVLSI'13, Paris,
France, May 2-4, 2013},
pages = {319--320},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2483028.2483121},
doi = {10.1145/2483028.2483121},
timestamp = {Tue, 23 Jul 2019 15:03:09 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/NaveG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/YavitsMG13a,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {The Effect of Communication and Synchronization on Amdahl Law in Multicore
Systems},
journal = {CoRR},
volume = {abs/1306.3302},
year = {2013},
url = {http://arxiv.org/abs/1306.3302},
eprinttype = {arXiv},
eprint = {1306.3302},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/YavitsMG13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/YavitsMG13b,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {Thermal analysis of 3D associative processor},
journal = {CoRR},
volume = {abs/1307.3853},
year = {2013},
url = {http://arxiv.org/abs/1307.3853},
eprinttype = {arXiv},
eprint = {1307.3853},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/YavitsMG13b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/YavitsMG13c,
author = {Leonid Yavits and
Amir Morad and
Ran Ginosar},
title = {3D Cache Hierarchy Optimization},
journal = {CoRR},
volume = {abs/1311.1667},
year = {2013},
url = {http://arxiv.org/abs/1311.1667},
eprinttype = {arXiv},
eprint = {1311.1667},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/YavitsMG13c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpcc/AvronG12,
author = {Itai Avron and
Ran Ginosar},
editor = {Geyong Min and
Jia Hu and
Lei (Chris) Liu and
Laurence Tianruo Yang and
Seetharami Seelam and
Laurent Lef{\`{e}}vre},
title = {Performance of a Hardware Scheduler for Many-core Architecture},
booktitle = {14th {IEEE} International Conference on High Performance Computing
and Communication {\&} 9th {IEEE} International Conference on
Embedded Software and Systems, {HPCC-ICESS} 2012, Liverpool, United
Kingdom, June 25-27, 2012},
pages = {151--160},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/HPCC.2012.29},
doi = {10.1109/HPCC.2012.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpcc/AvronG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/VaisbandFGK12,
author = {Inna Vaisband and
Eby G. Friedman and
Ran Ginosar and
Avinoam Kolodny},
title = {Energy metrics for power efficient crosslink and mesh topologies},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {1656--1659},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6271575},
doi = {10.1109/ISCAS.2012.6271575},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/VaisbandFGK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BeerG12,
author = {Salomon Beer and
Ran Ginosar},
editor = {Jos{\'{e}} L. Ayala and
Delong Shang and
Alex Yakovlev},
title = {An Extended Metastability Simulation Method for Synchronizer Characterization},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 22nd International Workshop, {PATMOS} 2012, Newcastle
upon Tyne, UK, September 4-6, 2012, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {7606},
pages = {42--51},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-36157-9\_5},
doi = {10.1007/978-3-642-36157-9\_5},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BeerG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/NaveG12,
author = {Eyal{-}Itzhak Nave and
Ran Ginosar},
editor = {Jos{\'{e}} L. Ayala and
Delong Shang and
Alex Yakovlev},
title = {{TCP} Window Based {DVFS} for Low Power Network Controller SoC},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 22nd International Workshop, {PATMOS} 2012, Newcastle
upon Tyne, UK, September 4-6, 2012, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {7606},
pages = {83--92},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-36157-9\_9},
doi = {10.1007/978-3-642-36157-9\_9},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/NaveG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/Ginosar11,
author = {Ran Ginosar},
title = {Metastability and Synchronizers: {A} Tutorial},
journal = {{IEEE} Des. Test Comput.},
volume = {28},
number = {5},
pages = {23--35},
year = {2011},
url = {https://doi.org/10.1109/MDT.2011.113},
doi = {10.1109/MDT.2011.113},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/Ginosar11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/VainbrandG11,
author = {Dmitri Vainbrand and
Ran Ginosar},
title = {Scalable network-on-chip architecture for configurable neural networks},
journal = {Microprocess. Microsystems},
volume = {35},
number = {2},
pages = {152--166},
year = {2011},
url = {https://doi.org/10.1016/j.micpro.2010.08.005},
doi = {10.1016/J.MICPRO.2010.08.005},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/VainbrandG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/BeerGPDK11,
author = {Salomon Beer and
Ran Ginosar and
Michael Priel and
Rostislav (Reuven) Dobkin and
Avinoam Kolodny},
title = {An on-chip metastability measurement circuit to characterize synchronization
behavior in 65nm},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2011), May
15-19 2011, Rio de Janeiro, Brazil},
pages = {2593--2596},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISCAS.2011.5938135},
doi = {10.1109/ISCAS.2011.5938135},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/BeerGPDK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/nocs/2011,
editor = {Radu Marculescu and
Michael Kishinevsky and
Ran Ginosar and
Karam S. Chatha},
title = {{NOCS} 2011, Fifth {ACM/IEEE} International Symposium on Networks-on-Chip,
Pittsburgh, Pennsylvania, USA, May 1-4, 2011},
publisher = {{ACM/IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1145/1999946},
doi = {10.1145/1999946},
isbn = {978-1-4503-0720-8},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nocs/2011.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MorgenshteinFGK10,
author = {Arkadiy Morgenshtein and
Eby G. Friedman and
Ran Ginosar and
Avinoam Kolodny},
title = {Unified Logical Effort - {A} Method for Delay Evaluation and Minimization
in Logic Paths With {RC} Interconnect},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {5},
pages = {689--696},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2009.2014239},
doi = {10.1109/TVLSI.2009.2014239},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MorgenshteinFGK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DobkinMKG10,
author = {Rostislav (Reuven) Dobkin and
Michael Moyal and
Avinoam Kolodny and
Ran Ginosar},
title = {Asynchronous Current Mode Serial Communication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {7},
pages = {1107--1117},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2009.2020859},
doi = {10.1109/TVLSI.2009.2020859},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DobkinMKG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MorgenshteinFGK10a,
author = {Arkadiy Morgenshtein and
Eby G. Friedman and
Ran Ginosar and
Avinoam Kolodny},
title = {Corrections to "Unified Logical Effort - {A} Method for Delay
Evaluation and Minimization in Logic Paths With {RC} Interconnect"
[May 10 689-696]},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {8},
pages = {1262},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2010.2052421},
doi = {10.1109/TVLSI.2010.2052421},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MorgenshteinFGK10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/BeerGPDK10,
author = {Salomon Beer and
Ran Ginosar and
Michael Priel and
Rostislav (Reuven) Dobkin and
Avinoam Kolodny},
title = {The Devolution of Synchronizers},
booktitle = {16th {IEEE} International Symposium on Asynchronous Circuits and Systems,
{ASYNC} 2010, Grenoble, France, 3-6 May 2010},
pages = {94--103},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ASYNC.2010.22},
doi = {10.1109/ASYNC.2010.22},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/BeerGPDK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AbdelhadiGKF10,
author = {Ameer Abdelhadi and
Ran Ginosar and
Avinoam Kolodny and
Eby G. Friedman},
editor = {R. Iris Bahar and
Fabrizio Lombardi and
David Atienza and
Erik Brunvand},
title = {Timing-driven variation-aware nonuniform clock mesh synthesis},
booktitle = {Proceedings of the 20th {ACM} Great Lakes Symposium on {VLSI} 2009,
Providence, Rhode Island, USA, May 16-18 2010},
pages = {15--20},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1785481.1785487},
doi = {10.1145/1785481.1785487},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/AbdelhadiGKF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/VainbrandG10,
author = {Dmitri Vainbrand and
Ran Ginosar},
title = {Network-on-Chip Architectures for Neural Networks},
booktitle = {{NOCS} 2010, Fourth {ACM/IEEE} International Symposium on Networks-on-Chip,
Grenoble, France, May 3-6, 2010},
pages = {135--144},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/NOCS.2010.23},
doi = {10.1109/NOCS.2010.23},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/VainbrandG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BermanGK10,
author = {Amit Berman and
Ran Ginosar and
Idit Keidar},
title = {Order is power: Selective Packet Interleaving for energy efficient
Networks-on-Chip},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {37--42},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642624},
doi = {10.1109/VLSISOC.2010.5642624},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BermanGK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DobkinGK09,
author = {Rostislav (Reuven) Dobkin and
Ran Ginosar and
Avinoam Kolodny},
title = {QNoC asynchronous router},
journal = {Integr.},
volume = {42},
number = {2},
pages = {103--115},
year = {2009},
url = {https://doi.org/10.1016/j.vlsi.2008.03.001},
doi = {10.1016/J.VLSI.2008.03.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DobkinGK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DobkinG09,
author = {Rostislav (Reuven) Dobkin and
Ran Ginosar},
title = {Two-phase synchronization with sub-cycle latency},
journal = {Integr.},
volume = {42},
number = {3},
pages = {367--375},
year = {2009},
url = {https://doi.org/10.1016/j.vlsi.2008.11.006},
doi = {10.1016/J.VLSI.2008.11.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DobkinG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/VaisbandGKF09,
author = {Inna Vaisband and
Ran Ginosar and
Avinoam Kolodny and
Eby G. Friedman},
editor = {Fabrizio Lombardi and
Sanjukta Bhanja and
Yehia Massoud and
R. Iris Bahar},
title = {Power efficient tree-based crosslinks for skew reduction},
booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
Boston Area, MA, USA, May 10-12 2009},
pages = {285--290},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1531542.1531609},
doi = {10.1145/1531542.1531609},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/VaisbandGKF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/infocom/BaronGK09,
author = {Asaf Baron and
Ran Ginosar and
Isaac Keslassy},
title = {The Capacity Allocation Paradox},
booktitle = {{INFOCOM} 2009. 28th {IEEE} International Conference on Computer Communications,
Joint Conference of the {IEEE} Computer and Communications Societies,
19-25 April 2009, Rio de Janeiro, Brazil},
pages = {1359--1367},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/INFCOM.2009.5062051},
doi = {10.1109/INFCOM.2009.5062051},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/infocom/BaronGK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/RotemMGW09,
author = {Efraim Rotem and
Avi Mendelson and
Ran Ginosar and
Uri C. Weiser},
editor = {David H. Albonesi and
Margaret Martonosi and
David I. August and
Jos{\'{e}} F. Mart{\'{\i}}nez},
title = {Multiple clock and voltage domains for chip multi processors},
booktitle = {42st Annual {IEEE/ACM} International Symposium on Microarchitecture
{(MICRO-42} 2009), December 12-16, 2009, New York, New York, {USA}},
pages = {459--468},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1669112.1669170},
doi = {10.1145/1669112.1669170},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/RotemMGW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ElyadaGW08,
author = {A. Elyada and
Ran Ginosar and
Uri C. Weiser},
title = {Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {9},
pages = {1243--1248},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.2000867},
doi = {10.1109/TVLSI.2008.2000867},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ElyadaGW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DobkinG08,
author = {Rostislav (Reuven) Dobkin and
Ran Ginosar},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Fast Universal Synchronizers},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {199--208},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_20},
doi = {10.1007/978-3-540-95948-9\_20},
timestamp = {Wed, 23 Feb 2022 16:05:31 +0100},
biburl = {https://dblp.org/rec/conf/patmos/DobkinG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/MorgenshteinFGK08,
author = {Arkadiy Morgenshtein and
Eby G. Friedman and
Ran Ginosar and
Avinoam Kolodny},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Timing optimization in logic with interconnect},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {19--26},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353615},
doi = {10.1145/1353610.1353615},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/MorgenshteinFGK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/DobkinMKG08,
author = {Rostislav (Reuven) Dobkin and
Arkadiy Morgenshtein and
Avinoam Kolodny and
Ran Ginosar},
editor = {Ion I. Mandoiu and
Andrew A. Kennings},
title = {Parallel vs. serial on-chip communication},
booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings},
pages = {43--50},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353610.1353620},
doi = {10.1145/1353610.1353620},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/DobkinMKG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tbe/PerelmanG07,
author = {Yevgeny Perelman and
Ran Ginosar},
title = {An Integrated System for Multichannel Neuronal Recording With Spike/LFP
Separation, Integrated {A/D} Conversion and Threshold Detection},
journal = {{IEEE} Trans. Biomed. Eng.},
volume = {54},
number = {1},
pages = {130--137},
year = {2007},
url = {https://doi.org/10.1109/TBME.2006.883732},
doi = {10.1109/TBME.2006.883732},
timestamp = {Wed, 02 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tbe/PerelmanG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tnn/RomEGLRBGH07,
author = {Rami Rom and
Jacob Erel and
Michael Glikson and
Randy A. Lieberman and
Kobi Rosenblum and
Ofer Binah and
Ran Ginosar and
David L. Hayes},
title = {Adaptive Cardiac Resynchronization Therapy Device Based on Spiking
Neurons Architecture and Reinforcement Learning Scheme},
journal = {{IEEE} Trans. Neural Networks},
volume = {18},
number = {2},
pages = {542--550},
year = {2007},
url = {https://doi.org/10.1109/TNN.2006.890806},
doi = {10.1109/TNN.2006.890806},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tnn/RomEGLRBGH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/GuzWBCGK07,
author = {Zvika Guz and
Isask'har Walter and
Evgeny Bolotin and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {Network Delays and Link Capacities in Application-Specific Wormhole
NoCs},
journal = {{VLSI} Design},
volume = {2007},
pages = {90941:1--90941:15},
year = {2007},
url = {https://doi.org/10.1155/2007/90941},
doi = {10.1155/2007/90941},
timestamp = {Thu, 16 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/GuzWBCGK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/DobkinPLGK07,
author = {Rostislav (Reuven) Dobkin and
Yevgeny Perelman and
Tuvia Liran and
Ran Ginosar and
Avinoam Kolodny},
title = {High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link},
booktitle = {13th {IEEE} International Symposium on Asynchronous Circuits and Systems
{(ASYNC} 2007), 12-14 March 2006, Berkeley, California, {USA}},
pages = {3--14},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASYNC.2007.20},
doi = {10.1109/ASYNC.2007.20},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/DobkinPLGK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BolotinCGK07,
author = {Evgeny Bolotin and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
editor = {Rudy Lauwereins and
Jan Madsen},
title = {Routing table minimization for irregular mesh NoCs},
booktitle = {2007 Design, Automation and Test in Europe Conference and Exposition,
{DATE} 2007, Nice, France, April 16-20, 2007},
pages = {942--947},
publisher = {{EDA} Consortium, San Jose, CA, {USA}},
year = {2007},
url = {https://doi.org/10.1109/DATE.2007.364414},
doi = {10.1109/DATE.2007.364414},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/BolotinCGK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/BolotinGCGK07,
author = {Evgeny Bolotin and
Zvika Guz and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {The Power of Priority: NoC Based Distributed Cache Coherency},
booktitle = {First International Symposium on Networks-on-Chips, {NOCS} 2007, 7-9
May 2007, Princeton, New Jersey, USA, Proceedings},
pages = {117--126},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/NOCS.2007.42},
doi = {10.1109/NOCS.2007.42},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/BolotinGCGK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/WalterCGK07,
author = {Isask'har Walter and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {Access Regulation to Hot-Modules in Wormhole NoCs},
booktitle = {First International Symposium on Networks-on-Chips, {NOCS} 2007, 7-9
May 2007, Princeton, New Jersey, USA, Proceedings},
pages = {137--148},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/NOCS.2007.8},
doi = {10.1109/NOCS.2007.8},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/WalterCGK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/DobkinGC07,
author = {Rostislav (Reuven) Dobkin and
Ran Ginosar and
Israel Cidon},
title = {QNoC Asynchronous Router with Dynamic Virtual Channel Allocation},
booktitle = {First International Symposium on Networks-on-Chips, {NOCS} 2007, 7-9
May 2007, Princeton, New Jersey, USA, Proceedings},
pages = {218},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/NOCS.2007.36},
doi = {10.1109/NOCS.2007.36},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/DobkinGC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/fmsd/FrankKG06,
author = {Uri Frank and
Tsachy Kapschitz and
Ran Ginosar},
title = {A predictive synchronizer for periodic clock domains},
journal = {Formal Methods Syst. Des.},
volume = {28},
number = {2},
pages = {171--186},
year = {2006},
url = {https://doi.org/10.1007/s10703-006-7843-9},
doi = {10.1007/S10703-006-7843-9},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/fmsd/FrankKG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/PerelmanG06,
author = {Yevgeny Perelman and
Ran Ginosar},
title = {A low-power inverted ladder D/a converter},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {53-II},
number = {6},
pages = {497--501},
year = {2006},
url = {https://doi.org/10.1109/TCSII.2006.875313},
doi = {10.1109/TCSII.2006.875313},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/PerelmanG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ObridkoG06,
author = {Ilya Obridko and
Ran Ginosar},
title = {Minimal Energy Asynchronous Dynamic Adders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {14},
number = {9},
pages = {1043--1047},
year = {2006},
url = {https://doi.org/10.1109/TVLSI.2006.884056},
doi = {10.1109/TVLSI.2006.884056},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ObridkoG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DobkinGS06,
author = {Rostislav (Reuven) Dobkin and
Ran Ginosar and
Christos P. Sotiriou},
title = {High Rate Data Synchronization in {GALS} SoCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {14},
number = {10},
pages = {1063--1074},
year = {2006},
url = {https://doi.org/10.1109/TVLSI.2006.884148},
doi = {10.1109/TVLSI.2006.884148},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DobkinGS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/DobkinGK06,
author = {Rostislav (Reuven) Dobkin and
Ran Ginosar and
Avinoam Kolodny},
title = {Fast Asynchronous Shift Register for Bit-Serial Communication},
booktitle = {12th {IEEE} International Symposium on Asynchronous Circuits and Systems
{(ASYNC} 2006), 13-15 March 2006, Grenoble, France},
pages = {117--127},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ASYNC.2006.17},
doi = {10.1109/ASYNC.2006.17},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/DobkinGK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GuzWBCGK06,
author = {Zvika Guz and
Isask'har Walter and
Evgeny Bolotin and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
editor = {Georges G. E. Gielen},
title = {Efficient link capacity and QoS design for network-on-chip},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {9--14},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.243951},
doi = {10.1109/DATE.2006.243951},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/GuzWBCGK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DobkinPG05,
author = {Rostislav (Reuven) Dobkin and
Michael Peleg and
Ran Ginosar},
title = {Parallel interleaver design and {VLSI} architecture for low-latency
{MAP} turbo decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {4},
pages = {427--438},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842916},
doi = {10.1109/TVLSI.2004.842916},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DobkinPG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/DobkinVFG05,
author = {Rostislav (Reuven) Dobkin and
Victoria Vishnyakov and
Eyal Friedman and
Ran Ginosar},
title = {An Asynchronous Router for Multiple Service Levels Networks on Chip},
booktitle = {11th International Symposium on Advanced Research in Asynchronous
Circuits and Systems {(ASYNC} 2005), 14-16 March 2005, New York, NY,
{USA}},
pages = {44--53},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ASYNC.2005.11},
doi = {10.1109/ASYNC.2005.11},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/DobkinVFG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/charme/KapschitzG05,
author = {Tsachy Kapschitz and
Ran Ginosar},
editor = {Dominique Borrione and
Wolfgang J. Paul},
title = {Formal Verification of Synchronizers},
booktitle = {Correct Hardware Design and Verification Methods, 13th {IFIP} {WG}
10.5 Advanced Research Working Conference, {CHARME} 2005, Saarbr{\"{u}}cken,
Germany, October 3-6, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3725},
pages = {359--362},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11560548\_31},
doi = {10.1007/11560548\_31},
timestamp = {Tue, 14 May 2019 10:00:39 +0200},
biburl = {https://dblp.org/rec/conf/charme/KapschitzG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MorgenshteinCGK05,
author = {Arkadiy Morgenshtein and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {Low-leakage repeaters for NoC interconnects},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {600--603},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464659},
doi = {10.1109/ISCAS.2005.1464659},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MorgenshteinCGK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ObridkoG05,
author = {Ilya Obridko and
Ran Ginosar},
title = {Low energy asynchronous architectures},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {5238--5241},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465816},
doi = {10.1109/ISCAS.2005.1465816},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ObridkoG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BolotinCGK04,
author = {Evgeny Bolotin and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {Cost considerations in network on chip},
journal = {Integr.},
volume = {38},
number = {1},
pages = {19--42},
year = {2004},
url = {https://doi.org/10.1016/j.vlsi.2004.03.006},
doi = {10.1016/J.VLSI.2004.03.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BolotinCGK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/BolotinCGK04,
author = {Evgeny Bolotin and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {QNoC: QoS architecture and design process for network on chip},
journal = {J. Syst. Archit.},
volume = {50},
number = {2-3},
pages = {105--128},
year = {2004},
url = {https://doi.org/10.1016/j.sysarc.2003.07.004},
doi = {10.1016/J.SYSARC.2003.07.004},
timestamp = {Tue, 19 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/BolotinCGK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MorgenshteinMG04,
author = {Arkadiy Morgenshtein and
Michael Moreinis and
Ran Ginosar},
title = {Asynchronous gate-diffusion-input {(GDI)} circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {12},
number = {8},
pages = {847--856},
year = {2004},
url = {https://doi.org/10.1109/TVLSI.2004.831474},
doi = {10.1109/TVLSI.2004.831474},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MorgenshteinMG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/DobkinGS04,
author = {Rostislav (Reuven) Dobkin and
Ran Ginosar and
Christos P. Sotiriou},
title = {Data Synchronization Issues in {GALS} SoCs},
booktitle = {10th International Symposium on Advanced Research in Asynchronous
Circuits and Systems {(ASYNC} 2004), 19-23 April 2004, Crete, Greece},
pages = {170--180},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ASYNC.2004.1299298},
doi = {10.1109/ASYNC.2004.1299298},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/DobkinGS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BranoverKG04,
author = {Alex Branover and
Rakefet Kol and
Ran Ginosar},
title = {Asynchronous Design By Conversion: Converting Synchronous Circuits
into Asynchronous Ones},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2004), 16-20 February 2004, Paris, France},
pages = {870--877},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DATE.2004.1268996},
doi = {10.1109/DATE.2004.1268996},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/BranoverKG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/ObridkoG04,
author = {Ilya Obridko and
Ran Ginosar},
title = {Low energy asynchronous adders},
booktitle = {Proceedings of the 2004 11th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2004, Tel Aviv, Israel, December 13-15,
2004},
pages = {164--167},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ICECS.2004.1399640},
doi = {10.1109/ICECS.2004.1399640},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/ObridkoG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/BolotinMCGK04,
author = {Evgeny Bolotin and
Arkadiy Morgenshtein and
Israel Cidon and
Ran Ginosar and
Avinoam Kolodny},
title = {Automatic hardware-efficient SoC integration by QoS network on chip},
booktitle = {Proceedings of the 2004 11th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2004, Tel Aviv, Israel, December 13-15,
2004},
pages = {479--482},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ICECS.2004.1399722},
doi = {10.1109/ICECS.2004.1399722},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/BolotinMCGK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MorgenshteinBCKG04,
author = {Arkadiy Morgenshtein and
Evgeny Bolotin and
Israel Cidon and
Avinoam Kolodny and
Ran Ginosar},
title = {Micro-modem - reliability solution for NoC communications},
booktitle = {Proceedings of the 2004 11th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2004, Tel Aviv, Israel, December 13-15,
2004},
pages = {483--486},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ICECS.2004.1399723},
doi = {10.1109/ICECS.2004.1399723},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/MorgenshteinBCKG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/issoc/MorgenshteinCKG04,
author = {Arkadiy Morgenshtein and
Israel Cidon and
Avinoam Kolodny and
Ran Ginosar},
title = {Comparative analysis of serial vs parallel links in NoC},
booktitle = {Proceedings of the 2004 International Symposium on System-on-Chip,
Tampere, Finland, November 16-18, 2004},
pages = {185--188},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ISSOC.2004.1411181},
doi = {10.1109/ISSOC.2004.1411181},
timestamp = {Mon, 09 Aug 2021 14:54:02 +0200},
biburl = {https://dblp.org/rec/conf/issoc/MorgenshteinCKG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/FrankG04,
author = {Uri Frank and
Ran Ginosar},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Predictive Synchronizer for Periodic Clock Domains},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {402--412},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_42},
doi = {10.1007/978-3-540-30205-6\_42},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/patmos/FrankG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/StevensGR03,
author = {Ken S. Stevens and
Ran Ginosar and
Shai Rotem},
title = {Relative timing [asynchronous design]},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {129--140},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.801606},
doi = {10.1109/TVLSI.2002.801606},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/StevensGR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ElboimKG03,
author = {Y. Elboim and
Avinoam Kolodny and
Ran Ginosar},
title = {A clock-tuning circuit for system-on-chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {616--626},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812371},
doi = {10.1109/TVLSI.2003.812371},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ElboimKG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/SemiatG03,
author = {Yaron Semiat and
Ran Ginosar},
title = {Timing Measurements of Synchronization Circuits},
booktitle = {9th International Symposium on Advanced Research in Asynchronous Circuits
and Systems {(ASYNC} 2003), 12-16 May 2003, Vancouver, BC, Canada},
pages = {68--77},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ASYNC.2003.1199167},
doi = {10.1109/ASYNC.2003.1199167},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/SemiatG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/Ginosar03,
author = {Ran Ginosar},
title = {Fourteen Ways to Fool Your Synchronizer},
booktitle = {9th International Symposium on Advanced Research in Asynchronous Circuits
and Systems {(ASYNC} 2003), 12-16 May 2003, Vancouver, BC, Canada},
pages = {89--97},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ASYNC.2003.1199169},
doi = {10.1109/ASYNC.2003.1199169},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/Ginosar03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pimrc/DobkinPG02,
author = {Rostislav (Reuven) Dobkin and
Michael Peleg and
Ran Ginosar},
title = {Parallel {VLSI} architecture for {MAP} turbo decoder},
booktitle = {The 13th {IEEE} International Symposium on Personal, Indoor and Mobile
Radio Communications, Lisboa, Portugal, September 15-18, 2002},
pages = {384--388},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/PIMRC.2002.1046727},
doi = {10.1109/PIMRC.2002.1046727},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/pimrc/DobkinPG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/StevensRGBMYKDR01,
author = {Kenneth S. Stevens and
Shai Rotem and
Ran Ginosar and
Peter A. Beerel and
Chris J. Myers and
Kenneth Y. Yun and
Rakefet Kol and
Charles Dike and
Marly Roncken},
title = {An asynchronous instruction length decoder},
journal = {{IEEE} J. Solid State Circuits},
volume = {36},
number = {2},
pages = {217--228},
year = {2001},
url = {https://doi.org/10.1109/4.902762},
doi = {10.1109/4.902762},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/StevensRGBMYKDR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/PerelmanG01,
author = {Yevgeny Perelman and
Ran Ginosar},
title = {A low-light-level sensor for medical diagnostic applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {36},
number = {10},
pages = {1553--1558},
year = {2001},
url = {https://doi.org/10.1109/4.953484},
doi = {10.1109/4.953484},
timestamp = {Mon, 04 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/PerelmanG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/RotemSDRAGKBMY99,
author = {Shai Rotem and
Ken S. Stevens and
Charles Dike and
Marly Roncken and
Boris Agapiev and
Ran Ginosar and
Rakefet Kol and
Peter A. Beerel and
Chris J. Myers and
Kenneth Y. Yun},
title = {{RAPPID:} An Asynchronous Instruction Length Decoder},
booktitle = {5th International Symposium on Advanced Research in Asynchronous Circuits
and Systems {(ASYNC} '99), 19-22 April 1999, Barcelona, Spain},
pages = {60--70},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ASYNC.1999.761523},
doi = {10.1109/ASYNC.1999.761523},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/RotemSDRAGKBMY99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/StevensRG99,
author = {Ken S. Stevens and
Shai Rotem and
Ran Ginosar},
title = {Relative Timing},
booktitle = {5th International Symposium on Advanced Research in Asynchronous Circuits
and Systems {(ASYNC} '99), 19-22 April 1999, Barcelona, Spain},
pages = {208--218},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ASYNC.1999.761535},
doi = {10.1109/ASYNC.1999.761535},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/StevensRG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/StevensRBCGKR99,
author = {Ken S. Stevens and
Shai Rotem and
Steven M. Burns and
Jordi Cortadella and
Ran Ginosar and
Michael Kishinevsky and
Marly Roncken},
editor = {Mary Jane Irwin},
title = {{CAD} Directions for High Performance Asynchronous Circuits},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {116--121},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.309893},
doi = {10.1145/309847.309893},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/StevensRBCGKR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jvcir/WolfGZ98,
author = {Stuart G. Wolf and
Ran Ginosar and
Yehoshua Y. Zeevi},
title = {Spatio-Chromatic Image Enhancement Based on a Model of Human Visual
Information Processing},
journal = {J. Vis. Commun. Image Represent.},
volume = {9},
number = {1},
pages = {25--37},
year = {1998},
url = {https://doi.org/10.1006/jvci.1998.0371},
doi = {10.1006/JVCI.1998.0371},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jvcir/WolfGZ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/ChouBGKMRSY98,
author = {Wei{-}Chun Chou and
Peter A. Beerel and
Ran Ginosar and
Rakefet Kol and
Chris J. Myers and
Shai Rotem and
Ken S. Stevens and
Kenneth Y. Yun},
title = {Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case
Optimized Transistor-Level Technology Mapping of Extended Burst-Mode
Circuits},
booktitle = {4th International Symposium on Advanced Research in Asynchronous Circuits
and Systems {(ASYNC} '98), 30 March - 2 April 1998, San Diego, CA,
{USA}},
pages = {80},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ASYNC.1998.666496},
doi = {10.1109/ASYNC.1998.666496},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/ChouBGKMRSY98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/GinosarK98,
author = {Ran Ginosar and
Rakefet Kol},
title = {Adaptive synchronization},
booktitle = {International Conference on Computer Design: {VLSI} in Computers and
Processors, {ICCD} 1998, Proceedings, 5-7 October, 1998, Austin, TX,
{USA}},
pages = {188--189},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICCD.1998.727042},
doi = {10.1109/ICCD.1998.727042},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/GinosarK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ics/KolG98,
author = {Rakefet Kol and
Ran Ginosar},
editor = {Greg K. Egan and
Richard P. Brent and
Dennis Gannon},
title = {\emph{Kin}: {A} High Performance Asynchronous Processor Architecture},
booktitle = {Proceedings of the 12th international conference on Supercomputing,
{ICS} 1998, Melbourne, Australia, July 13-17, 1998},
pages = {433--440},
publisher = {{ACM}},
year = {1998},
url = {https://doi.org/10.1145/277830.277937},
doi = {10.1145/277830.277937},
timestamp = {Tue, 06 Nov 2018 11:07:02 +0100},
biburl = {https://dblp.org/rec/conf/ics/KolG98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ZangiG98,
author = {Uzi Zangi and
Ran Ginosar},
editor = {Anantha P. Chandrakasan and
Sayfe Kiaei},
title = {A low power video processor},
booktitle = {Proceedings of the 1998 International Symposium on Low Power Electronics
and Design, 1998, Monterey, California, USA, August 10-12, 1998},
pages = {136--138},
publisher = {{ACM}},
year = {1998},
url = {https://doi.org/10.1145/280756.280835},
doi = {10.1145/280756.280835},
timestamp = {Mon, 27 Sep 2021 11:47:11 +0200},
biburl = {https://dblp.org/rec/conf/islped/ZangiG98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/KolG97,
author = {Rakefet Kol and
Ran Ginosar},
title = {A Double-Latched Asynchronous Pipeline},
booktitle = {Proceedings 1997 International Conference on Computer Design: {VLSI}
in Computers {\&} Processors, {ICCD} '97, Austin, Texas, USA,
October 12-15, 1997},
pages = {706--712},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICCD.1997.628942},
doi = {10.1109/ICCD.1997.628942},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/KolG97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/KolGS96,
author = {Rakefet Kol and
Ran Ginosar and
Goel Samuel},
title = {Statechart methodology for the design, validation, and synthesis of
large scale asynchronous systems},
booktitle = {2nd International Symposium on Advanced Research in Asynchronous Circuits
and Systems {(ASYNC} '96), March 18-21, 1996, Aizu-Wakamatsu, Fukushima,
Japan},
pages = {164--174},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ASYNC.1996.494448},
doi = {10.1109/ASYNC.1996.494448},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/KolGS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/DavidGY95,
author = {Ilana David and
Ran Ginosar and
Michael Yoeli},
title = {Self-timed is self-checking},
journal = {J. Electron. Test.},
volume = {6},
number = {2},
pages = {219--228},
year = {1995},
url = {https://doi.org/10.1007/BF00993088},
doi = {10.1007/BF00993088},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/DavidGY95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpr/ChenG94,
author = {Sarit Chen and
Ran Ginosar},
title = {Adaptive sensitivity {CCD} image sensor},
booktitle = {12th {IAPR} International Conference on Pattern Recognition, Conference
{C:} Signal Processing / Conference {D:} Parallel Computing, {ICPR}
1994, Jerusalem, Israel, 9-13 October, 1994, Volume 3},
pages = {363--365},
publisher = {{IEEE}},
year = {1994},
url = {https://doi.org/10.1109/ICPR.1994.577203},
doi = {10.1109/ICPR.1994.577203},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpr/ChenG94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpr/WolfGZ94,
author = {Stuart G. Wolf and
Ran Ginosar and
Yehoshua Y. Zeevi},
title = {Spatio-chromatic model for colour image processing},
booktitle = {12th {IAPR} International Conference on Pattern Recognition, Conference
{A:} Computer Vision {\&} Image Processing, {ICPR} 1994, Jerusalem,
Israel, 9-13 October, 1994, Volume 1},
pages = {599--601},
publisher = {{IEEE}},
year = {1994},
url = {https://doi.org/10.1109/ICPR.1994.576372},
doi = {10.1109/ICPR.1994.576372},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpr/WolfGZ94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RotmanG93,
author = {Alan Rotman and
Ran Ginosar},
title = {Control unit synthesis from a high-level language},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {12},
number = {1},
pages = {162--167},
year = {1993},
url = {https://doi.org/10.1109/43.184853},
doi = {10.1109/43.184853},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RotmanG93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip10-5/DavidGY93,
author = {Ilana David and
Ran Ginosar and
Michael Yoeli},
editor = {Stephen B. Furber and
Martyn Edwards},
title = {Self-Timed Architecture of a Reduced Instruction Set Computer},
booktitle = {Asynchronous Design Methodologies, Proceedings of the {IFIP} {WG10.5}
Working Conference on Asynchronous Design Methodologies, Manchester,
UK, 31 March - 2 April, 1993},
series = {{IFIP} Transactions},
volume = {{A-28}},
pages = {29--43},
publisher = {North-Holland},
year = {1993},
timestamp = {Wed, 17 Sep 2003 08:17:25 +0200},
biburl = {https://dblp.org/rec/conf/ifip10-5/DavidGY93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/DavidGY92,
author = {Ilana David and
Ran Ginosar and
Michael Yoeli},
title = {An Efficient Implementation of Boolean Functions as Self-Timed Circuits},
journal = {{IEEE} Trans. Computers},
volume = {41},
number = {1},
pages = {2--11},
year = {1992},
url = {https://doi.org/10.1109/12.123377},
doi = {10.1109/12.123377},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/DavidGY92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/DavidGY92a,
author = {Ilana David and
Ran Ginosar and
Michael Yoeli},
title = {Implementing Sequential Machines as Self-Timed Circuits},
journal = {{IEEE} Trans. Computers},
volume = {41},
number = {1},
pages = {12--17},
year = {1992},
url = {https://doi.org/10.1109/12.123378},
doi = {10.1109/12.123378},
timestamp = {Tue, 16 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/DavidGY92a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iclp/HarsatG91,
author = {Arie Harsat and
Ran Ginosar},
editor = {Koichi Furukawa},
title = {{CARMEL-4:} The Unify-Spawn Machine for {FCP}},
booktitle = {Logic Programming, Proceedings of the Eigth International Conference,
Paris, France, June 24-28, 1991},
pages = {840--854},
publisher = {{MIT} Press},
year = {1991},
timestamp = {Fri, 29 Nov 2013 14:57:24 +0100},
biburl = {https://dblp.org/rec/conf/iclp/HarsatG91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ngc/HarsatG90,
author = {Arie Harsat and
Ran Ginosar},
title = {{CARMEL-2:} {A} second generation {VLSI} architecture for Flat Concurrent
Prolog},
journal = {New Gener. Comput.},
volume = {7},
number = {2-3},
pages = {197--218},
year = {1990},
url = {https://doi.org/10.1007/BF03037206},
doi = {10.1007/BF03037206},
timestamp = {Thu, 14 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ngc/HarsatG90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/GinosarM90,
author = {Ran Ginosar and
Nick Michell},
title = {On the potential of asynchronous pipelined processors},
journal = {{SIGARCH} Comput. Archit. News},
volume = {18},
number = {4},
pages = {27--34},
year = {1990},
url = {https://doi.org/10.1145/121973.121977},
doi = {10.1145/121973.121977},
timestamp = {Thu, 08 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/GinosarM90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iclp/HarsatG90,
author = {Arie Harsat and
Ran Ginosar},
editor = {David H. D. Warren and
P{\'{e}}ter Szeredi},
title = {An Extended {RISC} Methodology and its Application to {FCP}},
booktitle = {Logic Programming, Proceedings of the Seventh International Conference,
Jerusalem, Israel, June 18-20, 1990},
pages = {67--82},
publisher = {{MIT} Press},
year = {1990},
timestamp = {Fri, 29 Nov 2013 14:57:24 +0100},
biburl = {https://dblp.org/rec/conf/iclp/HarsatG90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vcip/ZeeviG90,
author = {Yehoshua Y. Zeevi and
Ran Ginosar},
editor = {Murat Kunt},
title = {Foveating vision systems architecture: image acquisition and display},
booktitle = {Visual Communications and Image Processing '90: Fifth in a Series,
Visual Communications and Image Processing '90, Lausanne, Switzerland,
2-4 October 1990},
series = {{SPIE} Proceedings},
volume = {1360},
publisher = {{SPIE}},
year = {1990},
url = {https://doi.org/10.1117/12.24224},
doi = {10.1117/12.24224},
timestamp = {Fri, 11 Mar 2022 16:11:20 +0100},
biburl = {https://dblp.org/rec/conf/vcip/ZeeviG90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/GinosarE89,
author = {Ran Ginosar and
David Egozi},
title = {Topological comparison of perfect shuffle and hypercube},
journal = {Int. J. Parallel Program.},
volume = {18},
number = {1},
pages = {37--68},
year = {1989},
url = {https://doi.org/10.1007/BF01409745},
doi = {10.1007/BF01409745},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijpp/GinosarE89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/DavidGY89,
author = {Llana David and
Ran Ginosar and
Michael Yoeli},
title = {An efficient implementation of Boolean functions nd finite state machine
as self-timed circuit},
journal = {{SIGARCH} Comput. Archit. News},
volume = {17},
number = {6},
pages = {91--104},
year = {1989},
url = {https://doi.org/10.1145/77254.77262},
doi = {10.1145/77254.77262},
timestamp = {Thu, 08 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/DavidGY89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fgcs/HarsatG88,
author = {Arie Harsat and
Ran Ginosar},
title = {{CARMEL-2:} {A} Second Generation {VLSI} Architecture for Flat Concurrent
Prolog},
booktitle = {Proceedings of the International Conference on Fifth Generation Computer
Systems, {FGCS} 1988, Tokyo, Japan, November 28-December 2, 1988},
pages = {962--969},
publisher = {{OHMSHA} Ltd. Tokyo and Springer-Verlag},
year = {1988},
timestamp = {Mon, 05 Aug 2019 17:00:40 +0200},
biburl = {https://dblp.org/rec/conf/fgcs/HarsatG88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/GinosarH85,
author = {Ran Ginosar and
Dwight D. Hill},
title = {Design and Implementation of Switching Systems for Parallel Processors},
booktitle = {International Conference on Parallel Processing, ICPP'85, University
Park, PA, USA, August 1985},
pages = {674--680},
publisher = {{IEEE} Computer Society Press},
year = {1985},
timestamp = {Mon, 28 Jul 2014 17:06:01 +0200},
biburl = {https://dblp.org/rec/conf/icpp/GinosarH85.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/afips/ArdenG83,
author = {Bruce W. Arden and
Ran Ginosar},
title = {Performance evaluation of the {MP/C}},
booktitle = {American Federation of Information Processing Societies: 1983 National
Computer Conference, 16-19 May 1983, Anaheim, California, {USA}},
series = {{AFIPS} Conference Proceedings},
pages = {539--555},
publisher = {{AFIPS} Press},
year = {1983},
url = {https://doi.org/10.1145/1500676.1500744},
doi = {10.1145/1500676.1500744},
timestamp = {Wed, 14 Apr 2021 16:50:07 +0200},
biburl = {https://dblp.org/rec/conf/afips/ArdenG83.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ArdenG82,
author = {Bruce W. Arden and
Ran Ginosar},
title = {{MP/C:} {A} Multiprocessor/Computer Architecture},
journal = {{IEEE} Trans. Computers},
volume = {31},
number = {5},
pages = {455--473},
year = {1982},
url = {https://doi.org/10.1109/TC.1982.1676022},
doi = {10.1109/TC.1982.1676022},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/ArdenG82.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/ArdenG81,
author = {Bruce W. Arden and
Ran Ginosar},
editor = {Richard Y. Kain and
William R. Franta},
title = {{MP/C:} {A} Multiprocessor/Computer Architecture},
booktitle = {Proceedings of the 8th Annual Symposium on Computer Architecture,
Minneapolis, MN, USA, May 1981},
pages = {3--20},
publisher = {{IEEE} Computer Society},
year = {1981},
url = {http://dl.acm.org/citation.cfm?id=801863},
timestamp = {Fri, 09 Jul 2021 15:51:20 +0200},
biburl = {https://dblp.org/rec/conf/isca/ArdenG81.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/ArdenG81a,
author = {Bruce W. Arden and
Ran Ginosar},
editor = {Richard Y. Kain and
William R. Franta},
title = {A Single-Relation Module for a Data Base Machine},
booktitle = {Proceedings of the 8th Annual Symposium on Computer Architecture,
Minneapolis, MN, USA, May 1981},
pages = {227--238},
publisher = {{IEEE} Computer Society},
year = {1981},
url = {http://dl.acm.org/citation.cfm?id=801878},
timestamp = {Wed, 16 May 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isca/ArdenG81a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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