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ORCIDBibTeX records: Angel Fernandez Herrero
@article{DBLP:journals/ejasp/BayonHC12,
author = {Javier Gonzalez Bayon and
Angel Fernandez Herrero and
Carlos Carreras},
title = {A reduced complexity scheme for carrier frequency synchronization
in uplink 802.16e {OFDMA}},
journal = {{EURASIP} J. Adv. Signal Process.},
volume = {2012},
pages = {218},
year = {2012},
url = {https://doi.org/10.1186/1687-6180-2012-218},
doi = {10.1186/1687-6180-2012-218},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ejasp/BayonHC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/BayonHC12,
author = {Javier Gonzalez Bayon and
Angel Fernandez Herrero and
Carlos Carreras},
title = {Evaluation of Rapid Prototyping solutions for a 802.16d frequency
Offset estimation Scheme},
journal = {J. Circuits Syst. Comput.},
volume = {21},
number = {7},
year = {2012},
url = {https://doi.org/10.1142/S0218126612500569},
doi = {10.1142/S0218126612500569},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/BayonHC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ejasp/CaffarenaCLH10,
author = {Gabriel Caffarena and
Carlos Carreras and
Juan A. L{\'{o}}pez and
Angel Fernandez Herrero},
title = {{SQNR} Estimation of Fixed-Point {DSP} Algorithms},
journal = {{EURASIP} J. Adv. Signal Process.},
volume = {2010},
year = {2010},
url = {https://doi.org/10.1155/2010/171027},
doi = {10.1155/2010/171027},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ejasp/CaffarenaCLH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tce/Gonzalez-BayonHC10,
author = {Javier Gonzalez Bayon and
Angel Fernandez Herrero and
Carlos Carreras},
title = {Improved schemes for tracking residual frequency offset in {DVB-T}
systems},
journal = {{IEEE} Trans. Consumer Electron.},
volume = {56},
number = {2},
pages = {415--422},
year = {2010},
url = {https://doi.org/10.1109/TCE.2010.5505948},
doi = {10.1109/TCE.2010.5505948},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tce/Gonzalez-BayonHC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eusipco/CaffarenaLHC10,
author = {Gabriel Caffarena and
Juan A. L{\'{o}}pez and
Angel Fernandez Herrero and
Carlos Carreras},
title = {{SQNR} estimation of non-linear fixed-point algorithms},
booktitle = {18th European Signal Processing Conference, {EUSIPCO} 2010, Aalborg,
Denmark, August 23-27, 2010},
pages = {522--526},
publisher = {{IEEE}},
year = {2010},
url = {https://ieeexplore.ieee.org/document/7096318/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/eusipco/CaffarenaLHC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CaffarenaHLC10,
author = {Gabriel Caffarena and
Angel Fernandez Herrero and
Juan A. L{\'{o}}pez and
Carlos Carreras},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {Fast Fixed-Point Optimization of {DSP} Algorithms},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {182--205},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_8},
doi = {10.1007/978-3-642-28566-0\_8},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CaffarenaHLC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CaffarenaCLH10,
author = {Gabriel Caffarena and
Carlos Carreras and
Juan A. L{\'{o}}pez and
Angel Fernandez Herrero},
title = {Fast fixed-point optimization of {DSP} algorithms},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {195--200},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642659},
doi = {10.1109/VLSISOC.2010.5642659},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CaffarenaCLH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Jimenez-PachecoHC08,
author = {Alberto Jimenez{-}Pacheco and
Angel Fernandez Herrero and
Francisco Javier Casaj{\'{u}}s{-}Quir{\'{o}}s},
title = {Design and Implementation of a Hardware Module for {MIMO} Decoding
in a 4G Wireless Receiver},
journal = {{VLSI} Design},
volume = {2008},
pages = {312614:1--312614:8},
year = {2008},
url = {https://doi.org/10.1155/2008/312614},
doi = {10.1155/2008/312614},
timestamp = {Sat, 24 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/Jimenez-PachecoHC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iadis/HerreroEL08,
author = {Angel Fernandez Herrero and
Ignacio Elguez{\'{a}}bal and
Marisa L{\'{o}}pez{-}Vallejo},
editor = {Miguel Baptista Nunes and
Maggie McPherson},
title = {A Web-Based Environment Providing Remote Access To {FPGA} Platforms
For Teaching Digital Hardware Design},
booktitle = {{IADIS} International Conference e-Learning 2008, Amsterdam, The Netherlands,
July 22-25, 2008. Proceedings},
pages = {161--165},
publisher = {{IADIS}},
year = {2008},
timestamp = {Sun, 01 Mar 2009 21:54:10 +0100},
biburl = {https://dblp.org/rec/conf/iadis/HerreroEL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/HerreroJCC06,
author = {Angel Fernandez Herrero and
Alberto Jimenez{-}Pacheco and
Gabriel Caffarena and
Javier Casaj{\'{u}}s{-}Quir{\'{o}}s},
title = {Design and Implementation of a Hardware Module for Equalisation in
{A} 4G {MIMO} Receiver},
booktitle = {Proceedings of the 2006 International Conference on Field Programmable
Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},
pages = {1--4},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPL.2006.311309},
doi = {10.1109/FPL.2006.311309},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/HerreroJCC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/Jimenez-PachecoHC06,
author = {Alberto Jimenez{-}Pacheco and
Angel Fernandez Herrero and
Javier Casaj{\'{u}}s{-}Quir{\'{o}}s},
title = {Design and Implementation in {FPGA} of a {MIMO} Decoder for a 4G Wireless
Receiver},
booktitle = {13th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2006, Nice, France, December 10-13, 2006},
pages = {974--977},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ICECS.2006.379953},
doi = {10.1109/ICECS.2006.379953},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/Jimenez-PachecoHC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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