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ORCIDBibTeX records: Masaaki Higashitani
@article{DBLP:journals/jssc/LiuYSCLBYZYOSACGHKLMNPPSWYNTHMGTYOOTIF14,
author = {Tz{-}Yi Liu and
Tian Hong Yan and
Roy Scheuerlein and
Yingchang Chen and
Jeffrey KoonYee Lee and
Gopinath Balakrishnan and
Gordon Yee and
Henry Zhang and
Alex Yap and
Jingwen Ouyang and
Takahiko Sasaki and
Ali Al{-}Shamma and
Chin{-}Yu Chen and
Mayank Gupta and
Greg Hilton and
Achal Kathuria and
Vincent Lai and
Masahide Matsumoto and
Anurag Nigam and
Anil Pai and
Jayesh Pakhale and
Chang Hua Siau and
Xiaoxia Wu and
Yibo Yin and
Nicolas Nagel and
Yoichiro Tanaka and
Masaaki Higashitani and
Tim Minvielle and
Chandu Gorla and
Takayuki Tsukamoto and
Takeshi Yamaguchi and
Mutsumi Okajima and
Takayuki Okamura and
Satoru Takase and
Hirofumi Inoue and
Luca Fasoli},
title = {A 130.7-mm\({}^{\mbox{2}}\) 2-Layer 32-Gb ReRAM Memory Device in 24-nm
Technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {49},
number = {1},
pages = {140--153},
year = {2014},
url = {https://doi.org/10.1109/JSSC.2013.2280296},
doi = {10.1109/JSSC.2013.2280296},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/LiuYSCLBYZYOSACGHKLMNPPSWYNTHMGTYOOTIF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiuYSCLBYZYOSAACGHJKLMMNPPSWYPKHWNTHMGTYOOTHIFMSQ13,
author = {Tz{-}Yi Liu and
Tian Hong Yan and
Roy Scheuerlein and
Yingchang Chen and
Jeffrey KoonYee Lee and
Gopinath Balakrishnan and
Gordon Yee and
Henry Zhang and
Alex Yap and
Jingwen Ouyang and
Takahiko Sasaki and
Sravanti Addepalli and
Ali Al{-}Shamma and
Chin{-}Yu Chen and
Mayank Gupta and
Greg Hilton and
Saurabh Joshi and
Achal Kathuria and
Vincent Lai and
Deep Masiwal and
Masahide Matsumoto and
Anurag Nigam and
Anil Pai and
Jayesh Pakhale and
Chang Hua Siau and
Xiaoxia Wu and
Ronald Yin and
Liping Peng and
Jang Yong Kang and
Sharon Huynh and
Huijuan Wang and
Nicolas Nagel and
Yoichiro Tanaka and
Masaaki Higashitani and
Tim Minvielle and
Chandu Gorla and
Takayuki Tsukamoto and
Takeshi Yamaguchi and
Mutsumi Okajima and
Takayuki Okamura and
Satoru Takase and
Takahiko Hara and
Hirofumi Inoue and
Luca Fasoli and
Mehrdad Mofidi and
Ritu Shrivastava and
Khandker Quader},
title = {A 130.7mm\({}^{\mbox{2}}\) 2-layer 32Gb ReRAM memory device in 24nm
technology},
booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest
of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
17-21, 2013},
pages = {210--211},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISSCC.2013.6487703},
doi = {10.1109/ISSCC.2013.6487703},
timestamp = {Mon, 10 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LiuYSCLBYZYOSAACGHJKLMMNPPSWYPKHWNTHMGTYOOTHIFMSQ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/FukudaWMKSTKSTSOEINMMFYSNHTKMSYSSDWKMMNHLHMLMNH12,
author = {Koichi Fukuda and
Yoshihisa Watanabe and
Eiichi Makino and
Koichi Kawakami and
Jumpei Sato and
Teruo Takagiwa and
Naoaki Kanagawa and
Hitoshi Shiga and
Naoya Tokiwa and
Yoshihiko Shindo and
Takeshi Ogawa and
Toshiaki Edahiro and
Makoto Iwai and
Osamu Nagao and
Junji Musha and
Takatoshi Minamoto and
Yuka Furuta and
Kosuke Yanagidaira and
Yuya Suzuki and
Dai Nakamura and
Yoshikazu Hosomura and
Rieko Tanaka and
Hiromitsu Komai and
Mai Muramoto and
Go Shikata and
Ayako Yuminaka and
Kiyofumi Sakurai and
Manabu Sakai and
Hong Ding and
Mitsuyuki Watanabe and
Yosuke Kato and
Toru Miwa and
Alex Mak and
Masaru Nakamichi and
Gertjan Hemink and
Dana Lee and
Masaaki Higashitani and
Brian Murphy and
Bo Lei and
Yasuhiko Matsunaga and
Kiyomi Naruke and
Takahiko Hara},
title = {A 151-mm\({}^{\mbox{2}}\) 64-Gb 2 Bit/Cell {NAND} Flash Memory in
24-nm {CMOS} Technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {1},
pages = {75--84},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2011.2164711},
doi = {10.1109/JSSC.2011.2164711},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/FukudaWMKSTKSTSOEINMMFYSNHTKMSYSSDWKMMNHLHMLMNH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ShibataKH12,
author = {Noboru Shibata and
Kazushige Kanda and
Toshiki Hisada and
Katsuaki Isobe and
Manabu Sato and
Yui Shimizu and
Takahiro Shimizu and
Takahiro Sugimoto and
Tomohiro Kobayashi and
Kazuko Inuzuka and
Naoaki Kanagawa and
Yasuyuki Kajitani and
Takeshi Ogawa and
J. Nakai and
Kiyoaki Iwasa and
Masatsugu Kojima and
Toshihiro Suzuki and
Yuya Suzuki and
Shintaro Sakai and
Tomofumi Fujimura and
Yuko Utsunomiya and
Toshifumi Hashimoto and
Makoto Miakashi and
Naoki Kobayashi and
M. Inagaki and
Yuuki Matsumoto and
Satoshi Inoue and
Yoshinao Suzuki and
D. He and
Yasuhiko Honda and
Junji Musha and
Masaki Nakagawa and
Mitsuaki Honma and
Naofumi Abiko and
Mitsumasa Koyanagi and
Masahiro Yoshihara and
Kazumi Ino and
Mitsuhiro Noguchi and
Teruhiko Kamei and
Yosuke Kato and
Shingo Zaitsu and
Hiroaki Nasu and
Takuya Ariki and
Hardwell Chibvongodze and
Mitsuyuki Watanabe and
Hong Ding and
Naoki Ookuma and
Ryuji Yamashita and
G. Liang and
Gertjan Hemink and
Farookh Moogat and
Cuong Trinh and
Masaaki Higashitani and
Tuan Pham and
Kousuke Kanazawa},
title = {A 19nm 112.8mm\({}^{\mbox{2}}\) 64Gb multi-level flash memory with
400Mb/s/pin 1.8V Toggle Mode interface},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {422--424},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6177073},
doi = {10.1109/ISSCC.2012.6177073},
timestamp = {Wed, 10 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ShibataKH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiLO12,
author = {Yan Li and
Seungpil Lee and
Ken Oowada and
Hao Nguyen and
Qui Nguyen and
Nima Mokhlesi and
Cynthia Hsu and
Jason Li and
Venky Ramachandra and
Teruhiko Kamei and
Masaaki Higashitani and
Tuan Pham and
Mitsuaki Honma and
Yoshihisa Watanabe and
Kazumi Ino and
Binh Le and
Byungki Woo and
Khin Htoo and
Taiyuan Tseng and
Long Pham and
Frank Tsai and
Kwang{-}Ho Kim and
Yi{-}Chieh Chen and
Min She and
Jonghak Yuh and
Alex Chu and
Chen Chen and
Ruchi Puri and
Hung{-}Szu Lin and
Yi{-}Fang Chen and
William Mak and
Jonathan Huynh and
Jim Chan and
Mitsuyuki Watanabe and
Daniel Yang and
Grishma Shah and
Pavithra Souriraj and
Dinesh Tadepalli and
Tenugu Suman and
Ray Gao and
Viski Popuri and
Behdad Azarbayjani and
Ravindra Madpur and
James Lan and
Emilio Yero and
Feng Pan and
Patrick Hong and
Jang Yong Kang and
Farookh Moogat and
Yupin Fong and
Raul Cernea and
Sharon Huynh and
Cuong Trinh and
Mehrdad Mofidi and
Ritu Shrivastava and
Khandker Quader},
title = {128Gb 3b/cell {NAND} flash memory in 19nm technology with 18MB/s write
rate and 400Mb/s toggle mode},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {436--437},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6177080},
doi = {10.1109/ISSCC.2012.6177080},
timestamp = {Thu, 15 Mar 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/LiLO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FukudaWMKSTKSTSEOINMMYSNHKFMTSYSSDWKMMNHLHMLMNH11,
author = {Koichi Fukuda and
Yoshihisa Watanabe and
Eiichi Makino and
Koichi Kawakami and
Jumpei Sato and
Teruo Takagiwa and
Naoaki Kanagawa and
Hitoshi Shiga and
Naoya Tokiwa and
Yoshihiko Shindo and
Toshiaki Edahiro and
Takeshi Ogawa and
Makoto Iwai and
Osamu Nagao and
Junji Musha and
Takatoshi Minamoto and
Kosuke Yanagidaira and
Yuya Suzuki and
Dai Nakamura and
Yoshikazu Hosomura and
Hiromitsu Komai and
Yuka Furuta and
Mai Muramoto and
Rieko Tanaka and
Go Shikata and
Ayako Yuminaka and
Kiyofumi Sakurai and
Manabu Sakai and
Hong Ding and
Mitsuyuki Watanabe and
Yosuke Kato and
Toru Miwa and
Alex Mak and
Masaru Nakamichi and
Gertjan Hemink and
Dana Lee and
Masaaki Higashitani and
Brian Murphy and
Bo Lei and
Yasuhiko Matsunaga and
Kiyomi Naruke and
Takahiko Hara},
title = {A 151mm\({}^{\mbox{2}}\) 64Gb {MLC} {NAND} flash memory in 24nm {CMOS}
technology},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
2011},
pages = {198--199},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISSCC.2011.5746280},
doi = {10.1109/ISSCC.2011.5746280},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FukudaWMKSTKSTSEOINMMYSNHKFMTSYSSDWKMMNHLHMLMNH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/CerneaPMCLLTTN009,
author = {Raul Cernea and
Long Pham and
Farookh Moogat and
Siu Lung Chan and
Binh Le and
Yan Li and
Shouchang Tsao and
Taiyuan Tseng and
Khanh Nguyen and
Jason Li and
Jayson Hu and
Jonghak Yuh and
Cynthia Hsu and
Fanglin Zhang and
Teruhiko Kamei and
Hiroaki Nasu and
Phil Kliza and
Khin Htoo and
Jeffrey Lutze and
Yingda Dong and
Masaaki Higashitani and
Junhui Yang and
Hung{-}Szu Lin and
Vamshi Sakhamuri and
Alan Li and
Feng Pan and
Sridhar Yadala and
Subodh Taigor and
Kishan Pradhan and
James Lan and
Jim Chan and
Takumi Abe and
Yasuyuki Fukuda and
Hideo Mukai and
Koichi Kawakami and
Connie Liang and
Tommy Ip and
Shu{-}Fen Chang and
Jaggi Lakshmipathi and
Sharon Huynh and
Dimitris Pantelakis and
Mehrdad Mofidi and
Khandker Quader},
title = {A 34 MB/s {MLC} Write Throughput 16 Gb {NAND} With All Bit Line Architecture
on 56 nm Technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {1},
pages = {186--194},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2008.2007152},
doi = {10.1109/JSSC.2008.2007152},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/CerneaPMCLLTTN009.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/LiLFPKPSNMHKHYK09,
author = {Yan Li and
Seungpil Lee and
Yupin Fong and
Feng Pan and
Tien{-}Chien Kuo and
Jongmin Park and
Tapan Samaddar and
Hao Nguyen and
Man Mui and
Khin Htoo and
Teruhiko Kamei and
Masaaki Higashitani and
Emilio Yero and
Gyuwan Kwon and
Phil Kliza and
Jun Wan and
Tetsuya Kaneko and
Hiroshi Maejima and
Hitoshi Shiga and
Makoto Hamada and
Norihiro Fujita and
Kazunori Kanebako and
Eugene Tam and
Anne Koh and
Iris Lu and
Calvin Chia{-}Hong Kuo and
Trung Pham and
Jonathan Huynh and
Qui Nguyen and
Hardwell Chibvongodze and
Mitsuyuki Watanabe and
Ken Oowada and
Grishma Shah and
Byungki Woo and
Ray Gao and
Jim Chan and
James Lan and
Patrick Hong and
Liping Peng and
Debi Das and
Dhritiman Ghosh and
Vivek Kalluru and
Sanjay Kulkarni and
Raul{-}Adrian Cernea and
Sharon Huynh and
Dimitris Pantelakis and
Chi{-}Ming Wang and
Khandker Quader},
title = {A 16 Gb 3-Bit Per Cell {(X3)} {NAND} Flash Memory on 56 nm Technology
With 8 MB/s Write Rate},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {1},
pages = {195--207},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2008.2007154},
doi = {10.1109/JSSC.2008.2007154},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/LiLFPKPSNMHKHYK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TrinhSN09,
author = {Cuong Trinh and
Noboru Shibata and
Takeshi Nakano and
Mikio Ogawa and
Jumpei Sato and
Yoshikazu Takeyama and
Katsuaki Isobe and
Binh Le and
Farookh Moogat and
Nima Mokhlesi and
Kenji Kozakai and
Patrick Hong and
Teruhiko Kamei and
Kiyoaki Iwasa and
J. Nakai and
Takahiro Shimizu and
Mitsuaki Honma and
Shintaro Sakai and
Toshimasa Kawaai and
Satoru Hoshi and
Jonghak Yuh and
Cynthia Hsu and
Taiyuan Tseng and
Jason Li and
Jayson Hu and
M. Liu and
Shahzad Khalid and
J. Chen and
Mitsuyuki Watanabe and
Hung{-}Szu Lin and
Junhui Yang and
K. McKay and
Khanh Nguyen and
Tuan Pham and
Y. Matsuda and
K. Nakamura and
Kazunori Kanebako and
Susumu Yoshikawa and
W. Igarashi and
Atsushi Inoue and
T. Takahashi and
Yukio Komatsu and
C. Suzuki and
Kousuke Kanazawa and
Masaaki Higashitani and
Seungpil Lee and
T. Murai and
K. Nguyen and
James Lan and
Sharon Huynh and
Mark Murin and
Mark Shlick and
Menahem Lasser and
Raul Cernea and
Mehrdad Mofidi and
K. Schuegraf and
Khandker Quader},
title = {A 5.6MB/s 64Gb 4b/Cell {NAND} Flash memory in 43nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
2009},
pages = {246--247},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISSCC.2009.4977400},
doi = {10.1109/ISSCC.2009.4977400},
timestamp = {Wed, 24 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/TrinhSN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/CerneaPMCLLTTNLHPHZKNKHLDHYLSLPYTPLCAFMKLICLHPMQ08,
author = {Raul Cernea and
Long Pham and
Farookh Moogat and
Siu Lung Chan and
Binh Le and
Yan Li and
Shouchang Tsao and
Taiyuan Tseng and
Khanh Nguyen and
Jason Li and
Jayson Hu and
Jong Park and
Cynthia Hsu and
Fanglin Zhang and
Teruhiko Kamei and
Hiroaki Nasu and
Phil Kliza and
Khin Htoo and
Jeffery Lutze and
Yingda Dong and
Masaaki Higashitani and
Junhui Yang and
Hung{-}Szu Lin and
Vamshi Sakhamuri and
Alan Li and
Feng Pan and
Sridhar Yadala and
Subodh Taigor and
Kishan Pradhan and
James Lan and
Jim Chan and
Takumi Abe and
Yasuyuki Fukuda and
Hideo Mukai and
Koichi Kawakami and
Connie Liang and
Tommy Ip and
Shu{-}Fen Chang and
Jaggi Lakshmipathi and
Sharon Huynh and
Dimitris Pantelakis and
Mehrdad Mofidi and
Khandker Quader},
title = {A 34MB/s-Program-Throughput 16Gb {MLC} {NAND} with All-Bitline Architecture
in 56nm},
booktitle = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2008, Digest of Technical Papers, San Francisco, CA, USA, February
3-7, 2008},
pages = {420--421},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISSCC.2008.4523236},
doi = {10.1109/ISSCC.2008.4523236},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/CerneaPMCLLTTNLHPHZKNKHLDHYLSLPYTPLCAFMKLICLHPMQ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KandaKYHYMKMCTCLMTOKFTISNSOKYAHMNYHIKHMIO08,
author = {Kazushige Kanda and
Masaru Koyanagi and
Toshio Yamamura and
Koji Hosono and
Masahiro Yoshihara and
Toru Miwa and
Yosuke Kato and
Alex Mak and
Siu Lung Chan and
Frank Tsai and
Raul Cernea and
Binh Le and
Eiichi Makino and
Takashi Taira and
Hiroyuki Otake and
Norifumi Kajimura and
Susumu Fujimura and
Yoshiaki Takeuchi and
Mikihiko Itoh and
Masanobu Shirakawa and
Dai Nakamura and
Yuya Suzuki and
Yuki Okukawa and
Masatsugu Kojima and
Kazuhide Yoneya and
Takamichi Arizono and
Toshiki Hisada and
Shinji Miyamoto and
Mitsuhiro Noguchi and
Toshitake Yaegashi and
Masaaki Higashitani and
Fumitoshi Ito and
Teruhiko Kamei and
Gertjan Hemink and
Tooru Maruyama and
Kazumi Ino and
Shigeo Ohshima},
title = {A 120mm\({}^{\mbox{2}}\) 16Gb 4-MLC {NAND} Flash Memory with 43nm
{CMOS} Technology},
booktitle = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2008, Digest of Technical Papers, San Francisco, CA, USA, February
3-7, 2008},
pages = {430--431},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISSCC.2008.4523241},
doi = {10.1109/ISSCC.2008.4523241},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KandaKYHYMKMCTCLMTOKFTISNSOKYAHMNYHIKHMIO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiLFPKPSNMHKHYKKWKMSHFKTKLKPHNCWOSWGCLHPDGKKCHPWQ08,
author = {Yan Li and
Seungpil Lee and
Yupin Fong and
Feng Pan and
Tien{-}Chien Kuo and
Jong Park and
Tapan Samaddar and
Hao Nguyen and
Man Mui and
Khin Htoo and
Teruhiko Kamei and
Masaaki Higashitani and
Emilio Yero and
Gyuwan Kwon and
Phil Kliza and
Jun Wan and
Tetsuya Kaneko and
Hiroshi Maejima and
Hitoshi Shiga and
Makoto Hamada and
Norihiro Fujita and
Kazunori Kanebako and
Eugene Tam and
Anne Koh and
Iris Lu and
Calvin Chia{-}Hong Kuo and
Trung Pham and
Jonathan Huynh and
Qui Nguyen and
Hardwell Chibvongodze and
Mitsuyuki Watanabe and
Ken Oowada and
Grishma Shah and
Byungki Woo and
Ray Gao and
Jim Chan and
James Lan and
Patrick Hong and
Liping Peng and
Debi Das and
Dhritiman Ghosh and
Vivek Kalluru and
Sanjay Kulkarni and
Raul Cernea and
Sharon Huynh and
Dimitris Pantelakis and
Chi{-}Ming Wang and
Khandker Quader},
title = {A 16Gb 3b/ Cell {NAND} Flash Memory in 56nm with 8MB/s Write Rate},
booktitle = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2008, Digest of Technical Papers, San Francisco, CA, USA, February
3-7, 2008},
pages = {506--507},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISSCC.2008.4523279},
doi = {10.1109/ISSCC.2008.4523279},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LiLFPKPSNMHKHYKKWKMSHFKTKLKPHNCWOSWGCLHPDGKKCHPWQ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/TakeuchiKFOHSWF07,
author = {Ken Takeuchi and
Yasushi Kameda and
Susumu Fujimura and
Hiroyuki Otake and
Koji Hosono and
Hitoshi Shiga and
Yoshihisa Watanabe and
Takuya Futatsuyama and
Yoshihiko Shindo and
Masatsugu Kojima and
Makoto Iwai and
Masanobu Shirakawa and
Masayuki Ichige and
Kazuo Hatakeyama and
Shinichi Tanaka and
Teruhiko Kamei and
Jia{-}Yi Fu and
Adi Cernea and
Yan Li and
Masaaki Higashitani and
Gertjan Hemink and
Shinji Sato and
Ken Oowada and
Shih{-}Chung Lee and
Naoki Hayashida and
Jun Wan and
Jeffrey Lutze and
Shouchang Tsao and
Mehrdad Mofidi and
Kiyofumi Sakurai and
Naoya Tokiwa and
Hiroko Waki and
Yasumitsu Nozawa and
Kazuhisa Kanazawa and
Shigeo Ohshima},
title = {A 56-nm {CMOS} 99-mm\({}^{\mbox{2}}\) 8-Gb Multi-Level {NAND} Flash
Memory With 10-MB/s Program Throughput},
journal = {{IEEE} J. Solid State Circuits},
volume = {42},
number = {1},
pages = {219--232},
year = {2007},
url = {https://doi.org/10.1109/JSSC.2006.888299},
doi = {10.1109/JSSC.2006.888299},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/TakeuchiKFOHSWF07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HaraFKSHMNAKFTA06,
author = {Takahiko Hara and
Koichi Fukuda and
Kazuhisa Kanazawa and
Noboru Shibata and
Koji Hosono and
Hiroshi Maejima and
Michio Nakagawa and
Takumi Abe and
Masatsugu Kojima and
Masaki Fujiu and
Yoshiaki Takeuchi and
Kazumi Amemiya and
Midori Morooka and
Teruhiko Kamei and
Hiroaki Nasu and
Chi{-}Ming Wang and
Kiyofumi Sakurai and
Naoya Tokiwa and
Hiroko Waki and
Tohru Maruyama and
Susumu Yoshikawa and
Masaaki Higashitani and
Tuan D. Pham and
Yupin Fong and
Toshiharu Watanabe},
title = {A 146-mm\({}^{\mbox{2}}\) 8-gb multi-level {NAND} flash memory with
70-nm {CMOS} technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {41},
number = {1},
pages = {161--169},
year = {2006},
url = {https://doi.org/10.1109/JSSC.2005.859027},
doi = {10.1109/JSSC.2005.859027},
timestamp = {Fri, 22 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HaraFKSHMNAKFTA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TakeuchiKFOHSWF06,
author = {Ken Takeuchi and
Yasushi Kameda and
Susumu Fujimura and
Hiroyuki Otake and
Koji Hosono and
Hitoshi Shiga and
Yoshihisa Watanabe and
Takuya Futatsuyama and
Yoshihiko Shindo and
Masatsugu Kojima and
Makoto Iwai and
Masanobu Shirakawa and
Masayuki Ichige and
Kazuo Hatakeyama and
Shinichi Tanaka and
Teruhiko Kamei and
Jia{-}Yi Fu and
Adi Cernea and
Yan Li and
Masaaki Higashitani and
Gertjan Hemink and
Shinji Sato and
Ken Oowada and
Shih{-}Chung Lee and
Naoki Hayashida and
Jun Wan and
Jeffrey Lutze and
Shouchang Tsao and
Mehrdad Mofidi and
Kiyofumi Sakurai and
Naoya Tokiwa and
Hiroko Waki and
Yasumitsu Nozawa and
Kazuhisa Kanazawa and
Shigeo Ohshima},
title = {A 56nm {CMOS} 99mm2 8Gb Multi-level {NAND} Flash Memory with 10MB/s
Program Throughput},
booktitle = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
2006, Digest of Technical Papers, an Francisco, CA, USA, February
6-9, 2006},
pages = {507--516},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISSCC.2006.1696083},
doi = {10.1109/ISSCC.2006.1696083},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/TakeuchiKFOHSWF06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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