BibTeX records: Maria Antonia Iachino

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@inproceedings{DBLP:conf/ijcnn/MarraIM07,
  author       = {Salvatore Marra and
                  Maria Antonia Iachino and
                  Francesco Carlo Morabito},
  title        = {High Speed, Programmable Implementation of a Tanh-like Activation
                  Function and Its Derivative for Digital Neural Networks},
  booktitle    = {Proceedings of the International Joint Conference on Neural Networks,
                  {IJCNN} 2007, Celebrating 20 years of neural networks, Orlando, Florida,
                  USA, August 12-17, 2007},
  pages        = {506--511},
  publisher    = {{IEEE}},
  year         = {2007},
  url          = {https://doi.org/10.1109/IJCNN.2007.4371008},
  doi          = {10.1109/IJCNN.2007.4371008},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/ijcnn/MarraIM07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jcsc/PerriIC06,
  author       = {Stefania Perri and
                  Maria Antonia Iachino and
                  Pasquale Corsonello},
  title        = {Simd Multipliers for Accelerating Embedded Processors in {FPGAS}},
  journal      = {J. Circuits Syst. Comput.},
  volume       = {15},
  number       = {4},
  pages        = {537--550},
  year         = {2006},
  url          = {https://doi.org/10.1142/S0218126606003210},
  doi          = {10.1142/S0218126606003210},
  timestamp    = {Tue, 25 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jcsc/PerriIC06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@phdthesis{DBLP:phd/it/Iachino04,
  author       = {Maria Antonia Iachino},
  title        = {Arithmetic circuits for multimedia extension of FPGA-based processors},
  school       = {Mediterranea University of Reggio Calabria, Italy},
  year         = {2004},
  url          = {https://opac.bncf.firenze.sbn.it/bncf-prod/resource?uri=BNI0010467},
  timestamp    = {Sat, 06 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/phd/it/Iachino04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/PerriCILC04,
  author       = {Stefania Perri and
                  Pasquale Corsonello and
                  Maria Antonia Iachino and
                  Marco Lanuzza and
                  Giuseppe Cocorullo},
  title        = {Variable precision arithmetic circuits for FPGA-based multimedia processors},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {12},
  number       = {9},
  pages        = {995--999},
  year         = {2004},
  url          = {https://doi.org/10.1109/TVLSI.2004.833400},
  doi          = {10.1109/TVLSI.2004.833400},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/PerriCILC04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpl/CorsonelloPIC03,
  author       = {Pasquale Corsonello and
                  Stefania Perri and
                  Maria Antonia Iachino and
                  Giuseppe Cocorullo},
  editor       = {Peter Y. K. Cheung and
                  George A. Constantinides and
                  Jos{\'{e}} T. de Sousa},
  title        = {Variable Precision Multipliers for FPGA-Based Reconfigurable Computing
                  Systems},
  booktitle    = {Field Programmable Logic and Application, 13th International Conference,
                  {FPL} 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {2778},
  pages        = {661--669},
  publisher    = {Springer},
  year         = {2003},
  url          = {https://doi.org/10.1007/978-3-540-45234-8\_64},
  doi          = {10.1007/978-3-540-45234-8\_64},
  timestamp    = {Tue, 14 May 2019 10:00:48 +0200},
  biburl       = {https://dblp.org/rec/conf/fpl/CorsonelloPIC03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/icecsys/PerriIC02,
  author       = {Stefania Perri and
                  Maria Antonia Iachino and
                  Pasquale Corsonello},
  title        = {Speed-efficient wide adders for {VIRTEX} FPGAs},
  booktitle    = {Proceedings of the 2002 9th {IEEE} International Conference on Electronics,
                  Circuits and Systems, {ICECS} 2002, Dubrovnik, Croatia, September
                  15-18, 2002},
  pages        = {599--602},
  publisher    = {{IEEE}},
  year         = {2002},
  url          = {https://doi.org/10.1109/ICECS.2002.1046239},
  doi          = {10.1109/ICECS.2002.1046239},
  timestamp    = {Mon, 09 Aug 2021 14:54:04 +0200},
  biburl       = {https://dblp.org/rec/conf/icecsys/PerriIC02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}