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ORCIDBibTeX records: Guy Lemieux
@article{DBLP:journals/tecs/YoungHL23,
author = {May Young and
Alan J. Hu and
Guy G. F. Lemieux},
title = {Cache Abstraction for Data Race Detection in Heterogeneous Systems
with Non-coherent Accelerators},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {22},
number = {1},
pages = {6:1--6:25},
year = {2023},
url = {https://doi.org/10.1145/3535457},
doi = {10.1145/3535457},
timestamp = {Tue, 31 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tecs/YoungHL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ZhouPLI23,
author = {Zhonghua Zhou and
Yuxuan Pan and
Guy G. F. Lemieux and
Andr{\'{e}} Ivanov},
title = {{MEDUSA:} {A} Multi-Resolution Machine Learning Congestion Estimation
Method for 2D and 3D Global Routing},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {28},
number = {5},
pages = {73:1--73:25},
year = {2023},
url = {https://doi.org/10.1145/3590768},
doi = {10.1145/3590768},
timestamp = {Sat, 28 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/ZhouPLI23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/TatsumiFWSL22,
author = {Mariko Tatsumi and
Silviu{-}Ioan Filip and
Caroline White and
Olivier Sentieys and
Guy Lemieux},
title = {Mixing Low-Precision Formats in Multiply-Accumulate Units for {DNN}
Training},
booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT}
2022, Hong Kong, December 5-9, 2022},
pages = {1--9},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICFPT56656.2022.9974324},
doi = {10.1109/ICFPT56656.2022.9974324},
timestamp = {Wed, 21 Dec 2022 13:47:20 +0100},
biburl = {https://dblp.org/rec/conf/fpt/TatsumiFWSL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lctrts/YoungHL21,
author = {May Young and
Alan J. Hu and
Guy G. F. Lemieux},
editor = {J{\"{o}}rg Henkel and
Xu Liu},
title = {Cache abstraction for data race detection in heterogeneous systems
with non-coherent accelerators},
booktitle = {{LCTES} '21: 22nd {ACM} {SIGPLAN/SIGBED} International Conference
on Languages, Compilers, and Tools for Embedded Systems, Virtual Event,
Canada, 22 June, 2021},
pages = {151--162},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3461648.3463856},
doi = {10.1145/3461648.3463856},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/lctrts/YoungHL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/YangGRGLL20,
author = {Dingqing Yang and
Amin Ghasemazar and
Xiaowei Ren and
Maximilian Golub and
Guy Lemieux and
Mieszko Lis},
title = {Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network
Training},
booktitle = {53rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
{MICRO} 2020, Athens, Greece, October 17-21, 2020},
pages = {711--724},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MICRO50266.2020.00064},
doi = {10.1109/MICRO50266.2020.00064},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/YangGRGLL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2009-10976,
author = {Dingqing Yang and
Amin Ghasemazar and
Xiaowei Ren and
Maximilian Golub and
Guy Lemieux and
Mieszko Lis},
title = {Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network
Training},
journal = {CoRR},
volume = {abs/2009.10976},
year = {2020},
url = {https://arxiv.org/abs/2009.10976},
eprinttype = {arXiv},
eprint = {2009.10976},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2009-10976.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/OmidianL19,
author = {Hossein Omidian and
Guy G. F. Lemieux},
editor = {Ioannis Sourdis and
Christos{-}Savvas Bouganis and
Carlos {\'{A}}lvarez and
Leonel Antonio Toledo D{\'{\i}}az and
Pedro Valero{-}Lara and
Xavier Martorell},
title = {Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx
FPGAs},
booktitle = {29th International Conference on Field Programmable Logic and Applications,
{FPL} 2019, Barcelona, Spain, September 8-12, 2019},
pages = {391--396},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/FPL.2019.00068},
doi = {10.1109/FPL.2019.00068},
timestamp = {Sun, 22 Mar 2020 18:13:30 +0100},
biburl = {https://dblp.org/rec/conf/fpl/OmidianL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/OmidianL19,
author = {Hossein Omidian and
Guy G. F. Lemieux},
title = {Software-based Dynamic Overlays Require Fast, Fine-grained Partial
Reconfiguration},
booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
Japan, June 6-7, 2019},
pages = {13:1--13:6},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3337801.3337816},
doi = {10.1145/3337801.3337816},
timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
biburl = {https://dblp.org/rec/conf/heart/OmidianL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mlsys/GolubLL19,
author = {Maximilian Golub and
Guy Lemieux and
Mieszko Lis},
editor = {Ameet Talwalkar and
Virginia Smith and
Matei Zaharia},
title = {Full Deep Neural Network Training On {A} Pruned Weight Budget},
booktitle = {Proceedings of Machine Learning and Systems 2019, MLSys 2019, Stanford,
CA, USA, March 31 - April 2, 2019},
publisher = {mlsys.org},
year = {2019},
url = {https://proceedings.mlsys.org/book/260.pdf},
timestamp = {Thu, 18 Jun 2020 15:47:05 +0200},
biburl = {https://dblp.org/rec/conf/mlsys/GolubLL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1903-06630,
author = {Guy G. F. Lemieux and
Joe Edwards and
Joel Vandergriendt and
Aaron Severance and
Ryan De Iaco and
Abdullah Raouf and
Hussein Osman and
Tom Watzka and
Satwant Singh},
title = {TinBiNN: Tiny Binarized Neural Network Overlay in about 5, 000 4-LUTs
and 5mW},
journal = {CoRR},
volume = {abs/1903.06630},
year = {2019},
url = {http://arxiv.org/abs/1903.06630},
eprinttype = {arXiv},
eprint = {1903.06630},
timestamp = {Mon, 01 Apr 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1903-06630.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AbdelhadiLS18,
author = {Ameer M. S. Abdelhadi and
Guy G. F. Lemieux and
Lesley Shannon},
title = {Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable
Memories},
booktitle = {28th International Conference on Field Programmable Logic and Applications,
{FPL} 2018, Dublin, Ireland, August 27-31, 2018},
pages = {243--250},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/FPL.2018.00049},
doi = {10.1109/FPL.2018.00049},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/AbdelhadiLS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/OmidianIL18,
author = {Hossein Omidian and
Nick Ivanov and
Guy G. F. Lemieux},
title = {An Accelerated OpenVX Overlay for Pure Software Programmers},
booktitle = {International Conference on Field-Programmable Technology, {FPT} 2018,
Naha, Okinawa, Japan, December 10-14, 2018},
pages = {290--293},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/FPT.2018.00056},
doi = {10.1109/FPT.2018.00056},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/OmidianIL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1806-06949,
author = {Maximilian Golub and
Guy Lemieux and
Mieszko Lis},
title = {DropBack: Continuous Pruning During Training},
journal = {CoRR},
volume = {abs/1806.06949},
year = {2018},
url = {http://arxiv.org/abs/1806.06949},
eprinttype = {arXiv},
eprint = {1806.06949},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1806-06949.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/EdwardsL17,
author = {Joe Edwards and
Guy G. F. Lemieux},
title = {Real-time object detection in software with custom vector instructions
and algorithm changes},
booktitle = {28th {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2017, Seattle, WA, USA, July
10-12, 2017},
pages = {75--82},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ASAP.2017.7995262},
doi = {10.1109/ASAP.2017.7995262},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/EdwardsL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/OmidianL17,
author = {Hossein Omidian and
Guy G. F. Lemieux},
title = {Exploring automated space/time tradeoffs for OpenVX compute graphs},
booktitle = {International Conference on Field Programmable Technology, {FPT} 2017,
Melbourne, Australia, December 11-13, 2017},
pages = {152--159},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/FPT.2017.8280133},
doi = {10.1109/FPT.2017.8280133},
timestamp = {Mon, 17 Feb 2020 13:32:07 +0100},
biburl = {https://dblp.org/rec/conf/fpt/OmidianL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AbdelhadiL16,
author = {Ameer M. S. Abdelhadi and
Guy G. F. Lemieux},
title = {Modular Switched Multiported SRAM-Based Memories},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {3},
pages = {22:1--22:26},
year = {2016},
url = {https://doi.org/10.1145/2851506},
doi = {10.1145/2851506},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AbdelhadiL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/AbdelhadiL16,
author = {Ameer M. S. Abdelhadi and
Guy G. F. Lemieux},
title = {A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs},
booktitle = {24th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2016, Washington, DC, USA, May 1-3, 2016},
pages = {140--147},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/FCCM.2016.45},
doi = {10.1109/FCCM.2016.45},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/AbdelhadiL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/OmidianL16,
author = {Hossein Omidian and
Guy G. F. Lemieux},
title = {Automated Space/Time Scaling of Streaming Task Graph},
journal = {CoRR},
volume = {abs/1606.03717},
year = {2016},
url = {http://arxiv.org/abs/1606.03717},
eprinttype = {arXiv},
eprint = {1606.03717},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/OmidianL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MoctarLB15,
author = {Yehdhih Ould Mohammed Moctar and
Guy G. F. Lemieux and
Philip Brisk},
title = {Fast and Memory-Efficient Routing Algorithms for Field Programmable
Gate Arrays With Sparse Intracluster Routing Crossbars},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {34},
number = {12},
pages = {1928--1941},
year = {2015},
url = {https://doi.org/10.1109/TCAD.2015.2445739},
doi = {10.1109/TCAD.2015.2445739},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MoctarLB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/YueKL15,
author = {Michael Xi Yue and
Dirk Koch and
Guy G. F. Lemieux},
title = {Rapid Overlay Builder for Xilinx FPGAs},
booktitle = {23rd {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2015, Vancouver, BC, Canada, May 2-6, 2015},
pages = {17--20},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/FCCM.2015.48},
doi = {10.1109/FCCM.2015.48},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/YueKL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/AbdelhadiL15,
author = {Ameer M. S. Abdelhadi and
Guy G. F. Lemieux},
title = {Modular SRAM-Based Binary Content-Addressable Memories},
booktitle = {23rd {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2015, Vancouver, BC, Canada, May 2-6, 2015},
pages = {207--214},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/FCCM.2015.69},
doi = {10.1109/FCCM.2015.69},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/AbdelhadiL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SeveranceEL15,
author = {Aaron Severance and
Joe Edwards and
Guy G. F. Lemieux},
editor = {George A. Constantinides and
Deming Chen},
title = {Wavefront Skipping using BRAMs for Conditional Algorithms on Vector
Processors},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {171--180},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689072},
doi = {10.1145/2684746.2689072},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SeveranceEL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/TangL15,
author = {Shao Lin S. T. Tang and
Guy Lemieux},
editor = {George A. Constantinides and
Deming Chen},
title = {Area Optimization of Arithmetic Units by Component Sharing for FPGAs
(Abstract Only)},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {276},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689146},
doi = {10.1145/2684746.2689146},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/TangL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/AbdelhadiL14,
author = {Ameer Abdelhadi and
Guy G. F. Lemieux},
editor = {Vaughn Betz and
George A. Constantinides},
title = {Modular multi-ported SRAM-based memories},
booktitle = {The 2014 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} '14, Monterey, CA, {USA} - February 26 - 28, 2014},
pages = {35--44},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2554688.2554773},
doi = {10.1145/2554688.2554773},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/AbdelhadiL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SeveranceEOL14,
author = {Aaron Severance and
Joe Edwards and
Hossein Omidian and
Guy Lemieux},
editor = {Vaughn Betz and
George A. Constantinides},
title = {Soft vector processors with streaming pipelines},
booktitle = {The 2014 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} '14, Monterey, CA, {USA} - February 26 - 28, 2014},
pages = {117--126},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2554688.2554774},
doi = {10.1145/2554688.2554774},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SeveranceEOL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/AbdelhadiL14,
author = {Ameer M. S. Abdelhadi and
Guy G. F. Lemieux},
editor = {Jialin Chen and
Wenbo Yin and
Yuichiro Shibata and
Lingli Wang and
Hayden Kwok{-}Hay So and
Yuchun Ma},
title = {Deep and narrow binary content-addressable memories using FPGA-based
BRAMs},
booktitle = {2014 International Conference on Field-Programmable Technology, {FPT}
2014, Shanghai, China, December 10-12, 2014},
pages = {318--321},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPT.2014.7082808},
doi = {10.1109/FPT.2014.7082808},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/AbdelhadiL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/SeveranceL13,
author = {Aaron Severance and
Guy G. F. Lemieux},
title = {Embedded supercomputing in FPGAs with the VectorBlox {MXP} Matrix
Processor},
booktitle = {Proceedings of the International Conference on Hardware/Software Codesign
and System Synthesis, {CODES+ISSS} 2013, Montreal, QC, Canada, September
29 - October 4, 2013},
pages = {6:1--6:10},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CODES-ISSS.2013.6658993},
doi = {10.1109/CODES-ISSS.2013.6658993},
timestamp = {Wed, 16 Oct 2019 14:14:48 +0200},
biburl = {https://dblp.org/rec/conf/codes/SeveranceL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/BrantASTYL13,
author = {Alexander Brant and
Ameer Abdelhadi and
Douglas H. H. Sim and
Shao Lin Tang and
Michael Xi Yue and
Guy G. F. Lemieux},
title = {Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using
Razor},
booktitle = {21st {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2013, Seattle, WA, USA, April 28-30, 2013},
pages = {37--44},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/FCCM.2013.63},
doi = {10.1109/FCCM.2013.63},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/BrantASTYL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KochBL13,
author = {Dirk Koch and
Christian Beckhoff and
Guy G. F. Lemieux},
title = {An efficient {FPGA} overlay for portable custom instruction set extensions},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1--8},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645517},
doi = {10.1109/FPL.2013.6645517},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/KochBL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/SeveranceL13,
author = {Aaron Severance and
Guy G. F. Lemieux},
title = {TputCache: High-frequency, multi-way cache for high-throughput {FPGA}
applications},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1--6},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645537},
doi = {10.1109/FPL.2013.6645537},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/SeveranceL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/GrantSLF12,
author = {David Grant and
Graeme Smecher and
Guy G. F. Lemieux and
Rosemary Francis},
title = {Rapid Synthesis and Simulation of Computational Circuits in an {MPPA}},
journal = {J. Signal Process. Syst.},
volume = {67},
number = {1},
pages = {47--63},
year = {2012},
url = {https://doi.org/10.1007/s11265-010-0562-x},
doi = {10.1007/S11265-010-0562-X},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/GrantSLF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/BrantL12,
author = {Alexander Brant and
Guy G. F. Lemieux},
title = {{ZUMA:} An Open {FPGA} Overlay Architecture},
booktitle = {2012 {IEEE} 20th Annual International Symposium on Field-Programmable
Custom Computing Machines, {FCCM} 2012, 29 April - 1 May 2012, Toronto,
Ontario, Canada},
pages = {93--96},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/FCCM.2012.25},
doi = {10.1109/FCCM.2012.25},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/BrantL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/SeveranceL12,
author = {Aaron Severance and
Guy Lemieux},
title = {{VENICE:} {A} Compact Vector Processor for {FPGA} Applications},
booktitle = {2012 {IEEE} 20th Annual International Symposium on Field-Programmable
Custom Computing Machines, {FCCM} 2012, 29 April - 1 May 2012, Toronto,
Ontario, Canada},
pages = {245},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/FCCM.2012.55},
doi = {10.1109/FCCM.2012.55},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/SeveranceL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LiuSSL12,
author = {Zhiduo Liu and
Aaron Severance and
Satnam Singh and
Guy G. F. Lemieux},
editor = {Katherine Compton and
Brad L. Hutchings},
title = {Accelerator compiler for the {VENICE} vector processor},
booktitle = {Proceedings of the {ACM/SIGDA} 20th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2012, Monterey, California, USA,
February 22-24, 2012},
pages = {229--232},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2145694.2145732},
doi = {10.1145/2145694.2145732},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LiuSSL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MoctarGPILB12,
author = {Yehdhih Ould Mohammed Moctar and
Nithin George and
Hadi Parandeh{-}Afshar and
Paolo Ienne and
Guy G. F. Lemieux and
Philip Brisk},
editor = {Katherine Compton and
Brad L. Hutchings},
title = {Reducing the cost of floating-point mantissa alignment and normalization
in FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 20th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2012, Monterey, California, USA,
February 22-24, 2012},
pages = {255--264},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2145694.2145738},
doi = {10.1145/2145694.2145738},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MoctarGPILB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WangL12,
author = {Chris C. Wang and
Guy G. F. Lemieux},
editor = {Katherine Compton and
Brad L. Hutchings},
title = {Parallel {FPGA} placement based on individual {LUT} placement (abstract
only)},
booktitle = {Proceedings of the {ACM/SIGDA} 20th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2012, Monterey, California, USA,
February 22-24, 2012},
pages = {269},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2145694.2145754},
doi = {10.1145/2145694.2145754},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/WangL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/MoctarLB12,
author = {Yehdhih Ould Mohammed Moctar and
Guy G. F. Lemieux and
Philip Brisk},
editor = {Dirk Koch and
Satnam Singh and
Jim T{\o}rresen},
title = {Routing algorithms for {FPGAS} with sparse intra-cluster routing crossbars},
booktitle = {22nd International Conference on Field Programmable Logic and Applications
(FPL), Oslo, Norway, August 29-31, 2012},
pages = {91--98},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPL.2012.6339246},
doi = {10.1109/FPL.2012.6339246},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/MoctarLB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/BrantASL12,
author = {Alexander Brant and
Ameer Abdelhadi and
Aaron Severance and
Guy G. F. Lemieux},
title = {Pipeline frequency boosting: Hiding dual-ported block {RAM} latency
using intentional clock skew},
booktitle = {2012 International Conference on Field-Programmable Technology, {FPT}
2012, Seoul, Korea (South), December 10-12, 2012},
pages = {235--238},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPT.2012.6412140},
doi = {10.1109/FPT.2012.6412140},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/BrantASL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SeveranceL12,
author = {Aaron Severance and
Guy Lemieux},
title = {{VENICE:} {A} compact vector processor for {FPGA} applications},
booktitle = {2012 International Conference on Field-Programmable Technology, {FPT}
2012, Seoul, Korea (South), December 10-12, 2012},
pages = {261--268},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPT.2012.6412146},
doi = {10.1109/FPT.2012.6412146},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/SeveranceL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AhmedLW11,
author = {Usman Ahmed and
Guy G. Lemieux and
Steven J. E. Wilton},
title = {Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs
(MPSAs)},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {12},
pages = {2195--2208},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2010.2076841},
doi = {10.1109/TVLSI.2010.2076841},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AhmedLW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RoseL11,
author = {Jonathan Rose and
Guy G. Lemieux},
editor = {John Wawrzynek and
Katherine Compton},
title = {The role of FPGAs in a converged future with heterogeneous programmable
processors: pre-conference workshop},
booktitle = {Proceedings of the {ACM/SIGDA} 19th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2011, Monterey, California, USA,
February 27, March 1, 2011},
pages = {1--2},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1950413.1950415},
doi = {10.1145/1950413.1950415},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/RoseL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChouSBLSL11,
author = {Christopher Han{-}Yu Chou and
Aaron Severance and
Alex D. Brant and
Zhiduo Liu and
Saurabh Sant and
Guy G. Lemieux},
editor = {John Wawrzynek and
Katherine Compton},
title = {{VEGAS:} soft vector processor with scratchpad memory},
booktitle = {Proceedings of the {ACM/SIGDA} 19th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2011, Monterey, California, USA,
February 27, March 1, 2011},
pages = {15--24},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1950413.1950420},
doi = {10.1145/1950413.1950420},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ChouSBLSL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GrantWL11,
author = {David Grant and
Chris C. Wang and
Guy G. Lemieux},
editor = {John Wawrzynek and
Katherine Compton},
title = {A {CAD} framework for Malibu: an {FPGA} with time-multiplexed coarse-grained
elements},
booktitle = {Proceedings of the {ACM/SIGDA} 19th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2011, Monterey, California, USA,
February 27, March 1, 2011},
pages = {123--132},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1950413.1950441},
doi = {10.1145/1950413.1950441},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/GrantWL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WangL11,
author = {Chris C. Wang and
Guy G. Lemieux},
editor = {John Wawrzynek and
Katherine Compton},
title = {Scalable and deterministic timing-driven parallel placement for FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 19th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2011, Monterey, California, USA,
February 27, March 1, 2011},
pages = {153--162},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1950413.1950445},
doi = {10.1145/1950413.1950445},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/WangL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/SeveranceL11,
author = {Aaron Severance and
Guy Lemieux},
title = {{VENICE:} {A} compact vector processor for {FPGA} applications},
booktitle = {2011 {IEEE} Hot Chips 23 Symposium (HCS), Stanford, CA, USA, August
17-19, 2011},
pages = {1--5},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2011.7477515},
doi = {10.1109/HOTCHIPS.2011.7477515},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hotchips/SeveranceL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/AbdelhadiL11,
author = {Ameer Abdelhadi and
Guy G. F. Lemieux},
editor = {Peter M. Athanas and
J{\"{u}}rgen Becker and
Ren{\'{e}} Cumplido},
title = {Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating
{LUT} Input Permutations},
booktitle = {2011 International Conference on Reconfigurable Computing and FPGAs,
ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011},
pages = {20--26},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ReConFig.2011.20},
doi = {10.1109/RECONFIG.2011.20},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/reconfig/AbdelhadiL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/GoedersLW11,
author = {Jeffrey B. Goeders and
Guy G. F. Lemieux and
Steven J. E. Wilton},
editor = {Peter M. Athanas and
J{\"{u}}rgen Becker and
Ren{\'{e}} Cumplido},
title = {Deterministic Timing-Driven Parallel Placement by Simulated Annealing
Using Half-Box Window Decomposition},
booktitle = {2011 International Conference on Reconfigurable Computing and FPGAs,
ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011},
pages = {41--48},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ReConFig.2011.27},
doi = {10.1109/RECONFIG.2011.27},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/reconfig/GoedersLW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/AlimadadiSLMDP10,
author = {Mehdi Alimadadi and
Samad Sheikhaei and
Guy Lemieux and
Shahriar Mirabbasi and
William G. Dunford and
Patrick R. Palmer},
title = {A 4 GHz Non-Resonant Clock Driver With Inductor-Assisted Energy Return
to Power Grid},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {57-I},
number = {8},
pages = {2099--2108},
year = {2010},
url = {https://doi.org/10.1109/TCSI.2009.2037850},
doi = {10.1109/TCSI.2009.2037850},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/AlimadadiSLMDP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/AhmedLW10,
author = {Usman Ahmed and
Guy G. Lemieux and
Steven J. E. Wilton},
editor = {Peter Y. K. Cheung and
John Wawrzynek},
title = {The impact of interconnect architecture on via-programmed structured
ASICs (VPSAs)},
booktitle = {Proceedings of the {ACM/SIGDA} 18th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2010, Monterey, California, USA,
February 21-23, 2010},
pages = {263--272},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1723112.1723157},
doi = {10.1145/1723112.1723157},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/AhmedLW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YuECPL09,
author = {Jason Yu and
Christopher Eagleston and
Christopher Han{-}Yu Chou and
Maxime Perreault and
Guy G. Lemieux},
title = {Vector Processing as a Soft Processor Accelerator},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {12:1--12:34},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534922},
doi = {10.1145/1534916.1534922},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/YuECPL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/TeehanLG09,
author = {Paul Teehan and
Guy G. Lemieux and
Mark R. Greenstreet},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect
in 65nm FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {43--52},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508136},
doi = {10.1145/1508128.1508136},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/TeehanLG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HoL09,
author = {Johnny Tsung Lin Ho and
Guy G. Lemieux},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {PERG-Rx: a hardware pattern-matching engine supporting limited regular
expressions},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {257--260},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508171},
doi = {10.1145/1508128.1508171},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/HoL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/LeongL09,
author = {David Leong and
Guy G. Lemieux},
editor = {Martin Danek and
Jiri Kadlec and
Brent E. Nelson},
title = {Replace: An incremental placement algorithm for field programmable
gate arrays},
booktitle = {19th International Conference on Field Programmable Logic and Applications,
{FPL} 2009, August 31 - September 2, 2009, Prague, Czech Republic},
pages = {154--161},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/FPL.2009.5272520},
doi = {10.1109/FPL.2009.5272520},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/LeongL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/DongL09,
author = {Xiao Dong and
Guy G. F. Lemieux},
editor = {Neil W. Bergmann and
Oliver Diessel and
Lesley Shannon},
title = {{PGR:} Period and glitch reduction via clock skew scheduling, delay
padding and GlitchLess},
booktitle = {Proceedings of the 2009 International Conference on Field-Programmable
Technology, {FPT} 2009, Sydney, Australia, December 9-11, 2009},
pages = {88--95},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/FPT.2009.5377666},
doi = {10.1109/FPT.2009.5377666},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/DongL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/GrantSLF09,
author = {David Grant and
Graeme Smecher and
Guy Lemieux and
Rosemary Francis},
editor = {Neil W. Bergmann and
Oliver Diessel and
Lesley Shannon},
title = {Rapid synthesis and simulation of computational circuits in an {MPPA}},
booktitle = {Proceedings of the 2009 International Conference on Field-Programmable
Technology, {FPT} 2009, Sydney, Australia, December 9-11, 2009},
pages = {151--158},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/FPT.2009.5377655},
doi = {10.1109/FPT.2009.5377655},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/GrantSLF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/TeehanLG09,
author = {Paul Teehan and
Guy G. Lemieux and
Mark R. Greenstreet},
title = {Estimating reliability and throughput of source-synchronous wave-pipelined
interconnect},
booktitle = {Third International Symposium on Networks-on-Chips, {NOCS} 2009, May
10-13 2009, La Jolla, CA, {USA.} Proceedings},
pages = {234--243},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/NOCS.2009.5071472},
doi = {10.1109/NOCS.2009.5071472},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/TeehanLG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GrantL08,
author = {David Grant and
Guy G. Lemieux},
title = {Perturb+mutate: Semisynthetic circuit generation for incremental placement
and routing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {3},
pages = {16:1--16:24},
year = {2008},
url = {https://doi.org/10.1145/1391732.1391736},
doi = {10.1145/1391732.1391736},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GrantL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LamoureuxLW08,
author = {Julien Lamoureux and
Guy G. Lemieux and
Steven J. E. Wilton},
title = {GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment
and Glitch Filtering},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {11},
pages = {1521--1534},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.2001237},
doi = {10.1109/TVLSI.2008.2001237},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LamoureuxLW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/LeeLM08,
author = {Edmund Lee and
Guy Lemieux and
Shahriar Mirabbasi},
title = {Interconnect Driver Design for Long Wires in Field-Programmable Gate
Arrays},
journal = {J. Signal Process. Syst.},
volume = {51},
number = {1},
pages = {57--76},
year = {2008},
url = {https://doi.org/10.1007/s11265-007-0141-y},
doi = {10.1007/S11265-007-0141-Y},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/LeeLM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LemieuxE08,
author = {Guy G. Lemieux and
Tarek A. El{-}Ghazawi},
editor = {Mike Hutton and
Paul Chow},
title = {Designing with extreme parallelism},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {1--2},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344673},
doi = {10.1145/1344671.1344673},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LemieuxE08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/El-GhazawiL08,
author = {Tarek A. El{-}Ghazawi and
Guy G. Lemieux},
editor = {Mike Hutton and
Paul Chow},
title = {Extreme parallel architectures for the masses},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {127--128},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344691},
doi = {10.1145/1344671.1344691},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/El-GhazawiL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YuLE08,
author = {Jason Yu and
Guy G. Lemieux and
Christopher Eagleston},
editor = {Mike Hutton and
Paul Chow},
title = {Vector processing as a soft-core {CPU} accelerator},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {222--232},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344704},
doi = {10.1145/1344671.1344704},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YuLE08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/HoL08,
author = {Johnny Tsung Lin Ho and
Guy G. F. Lemieux},
editor = {Tarek A. El{-}Ghazawi and
Yao{-}Wen Chang and
Juinn{-}Dar Huang and
Proshanta Saha},
title = {{PERG:} {A} scalable FPGA-based pattern-matching engine with consolidated
Bloomier filters},
booktitle = {2008 International Conference on Field-Programmable Technology, {FPT}
2008, Taipei, Taiwan, December 7-10, 2008},
pages = {73--80},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPT.2008.4762368},
doi = {10.1109/FPT.2008.4762368},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/HoL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/AlimadadiSLMDP08,
author = {Mehdi Alimadadi and
Samad Sheikhaei and
Guy Lemieux and
Shahriar Mirabbasi and
William G. Dunford and
Patrick R. Palmer},
title = {Energy Recovery from High-Frequency Clocks Using {DC-DC} Converters},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2008, 7-9
April 2008, Montpellier, France},
pages = {162--167},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISVLSI.2008.102},
doi = {10.1109/ISVLSI.2008.102},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/AlimadadiSLMDP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/TeehanGL07,
author = {Paul Teehan and
Mark R. Greenstreet and
Guy G. Lemieux},
title = {A Survey and Taxonomy of {GALS} Design Styles},
journal = {{IEEE} Des. Test Comput.},
volume = {24},
number = {5},
pages = {418--428},
year = {2007},
url = {https://doi.org/10.1109/MDT.2007.151},
doi = {10.1109/MDT.2007.151},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/TeehanGL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LamoureuxLW07,
author = {Julien Lamoureux and
Guy G. Lemieux and
Steven J. E. Wilton},
editor = {Andr{\'{e}} DeHon and
Mike Hutton},
title = {GlitchLess: an active glitch minimization technique for FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 15th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2007, Monterey, California, USA,
February 18-20, 2007},
pages = {156--165},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1216919.1216946},
doi = {10.1145/1216919.1216946},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LamoureuxLW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YuL07,
author = {Jason Yu and
Guy Lemieux},
editor = {Hideharu Amano and
Andy Ye and
Takeshi Ikenaga},
title = {A Case for Soft Vector Processors in FPGAs},
booktitle = {2007 International Conference on Field-Programmable Technology, {ICFPT}
2007, Kitakyushu, Japan, December 12-14, 2007},
pages = {341--344},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FPT.2007.4439281},
doi = {10.1109/FPT.2007.4439281},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/YuL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/AlimadadiSLMP07,
author = {Mehdi Alimadadi and
Samad Sheikhaei and
Guy Lemieux and
Shahriar Mirabbasi and
Patrick R. Palmer},
title = {A 3GHz Switching {DC-DC} Converter Using Clock-Tree Charge-Recycling
in 90nm {CMOS} with Integrated Output Filter},
booktitle = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2007, Digest of Technical Papers, San Francisco, CA, USA, February
11-15, 2007},
pages = {532--620},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISSCC.2007.373529},
doi = {10.1109/ISSCC.2007.373529},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/AlimadadiSLMP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/YeagerCL07,
author = {David Yeager and
Darius Chiu and
Guy G. Lemieux},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {Congestion estimation and localization in {FPGAS:} a visual tool for
interconnect prediction},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {33--40},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231963},
doi = {10.1145/1231956.1231963},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/YeagerCL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pieee/SalehWMHGLPGI06,
author = {Resve A. Saleh and
Steven J. E. Wilton and
Shahriar Mirabbasi and
Alan J. Hu and
Mark R. Greenstreet and
Guy Lemieux and
Partha Pratim Pande and
Cristian Grecu and
Andr{\'{e}} Ivanov},
title = {System-on-Chip: Reuse and Integration},
journal = {Proc. {IEEE}},
volume = {94},
number = {6},
pages = {1050--1069},
year = {2006},
url = {https://doi.org/10.1109/JPROC.2006.873611},
doi = {10.1109/JPROC.2006.873611},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/pieee/SalehWMHGLPGI06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/GrantCL06,
author = {David Grant and
Scott Chin and
Guy G. Lemieux},
title = {Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing
Incremental Placement and Incremental Routing Tools},
booktitle = {Proceedings of the 2006 International Conference on Field Programmable
Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},
pages = {1--4},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPL.2006.311300},
doi = {10.1109/FPL.2006.311300},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/GrantCL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/0002LM06,
author = {Edmund Lee and
Guy Lemieux and
Shahriar Mirabbasi},
editor = {George A. Constantinides and
Wai{-}Kei Mak and
Phaophak Sirisuk and
Theerayod Wiangtong},
title = {Interconnect driver design for long wires in field-programmable gate
arrays},
booktitle = {2006 {IEEE} International Conference on Field Programmable Technology,
{FPT} 2006, Bangkok, Thailand, December 13-15, 2006},
pages = {89--96},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPT.2006.270299},
doi = {10.1109/FPT.2006.270299},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/0002LM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/GrantL06,
author = {David Grant and
Guy Lemieux},
editor = {George A. Constantinides and
Wai{-}Kei Mak and
Phaophak Sirisuk and
Theerayod Wiangtong},
title = {Perturber: semi-synthetic circuit generation using ancestor control
for testing incremental place and route},
booktitle = {2006 {IEEE} International Conference on Field Programmable Technology,
{FPT} 2006, Bangkok, Thailand, December 13-15, 2006},
pages = {189--196},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPT.2006.270311},
doi = {10.1109/FPT.2006.270311},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/GrantL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/TomLL06,
author = {Marvin Tom and
David Leong and
Guy G. Lemieux},
editor = {Soha Hassoun},
title = {Un/DoPack: re-clustering of large system-on-chip designs with interconnect
variation for low-cost FPGAs},
booktitle = {2006 International Conference on Computer-Aided Design, {ICCAD} 2006,
San Jose, CA, USA, November 5-9, 2006},
pages = {680--687},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1233501.1233643},
doi = {10.1145/1233501.1233643},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/TomLL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/AkenOvaLS05,
author = {Victor O. Aken'Ova and
Guy Lemieux and
Resve A. Saleh},
title = {An improved "soft" eFPGA design and implementation strategy},
booktitle = {Proceedings of the {IEEE} 2005 Custom Integrated Circuits Conference,
{CICC} 2005, DoubleTree Hotel, San Jose, California, USA, September
18-21, 2005},
pages = {179--182},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/CICC.2005.1568636},
doi = {10.1109/CICC.2005.1568636},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/AkenOvaLS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/TomL05,
author = {Marvin Tom and
Guy G. Lemieux},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Logic block clustering of large designs for channel-width constrained
FPGAs},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {726--731},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065770},
doi = {10.1145/1065579.1065770},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/TomL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YuL05,
author = {Anthony J. Yu and
Guy G. Lemieux},
editor = {Tero Rissa and
Steven J. E. Wilton and
Philip Heng Wai Leong},
title = {Defect-Tolerant {FPGA} Switch Block and Connection Block with Fine-Grain
Redundancy for Yield Enhancement},
booktitle = {Proceedings of the 2005 International Conference on Field Programmable
Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005},
pages = {255--262},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/FPL.2005.1515731},
doi = {10.1109/FPL.2005.1515731},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/YuL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YuL05,
author = {Anthony J. Yu and
Guy G. Lemieux},
editor = {Gordon J. Brebner and
Samarjit Chakraborty and
Weng{-}Fai Wong},
title = {{FPGA} Defect Tolerance: Impact of Granularity},
booktitle = {Proceedings of the 2005 {IEEE} International Conference on Field-Programmable
Technology, {FPT} 2005, 11-14 December 2005, Singapore},
pages = {189--196},
publisher = {{IEEE}},
year = {2005},
timestamp = {Tue, 19 Jun 2018 20:15:46 +0200},
biburl = {https://dblp.org/rec/conf/fpt/YuL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0016230,
author = {Guy Lemieux and
David A. Lewis},
title = {Design of interconnection networks for programmable logic},
publisher = {Kluwer},
year = {2004},
isbn = {978-1-4020-7700-5},
timestamp = {Thu, 14 Apr 2011 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0016230.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/Lemieux0TY04,
author = {Guy Lemieux and
Edmund Lee and
Marvin Tom and
Anthony J. Yu},
editor = {Oliver Diessel and
John Williams},
title = {Directional and single-driver wires in {FPGA} interconnect},
booktitle = {Proceedings of the 2004 {IEEE} International Conference on Field-Programmable
Technology, Brisbane, Australia, December 6-8, 2004},
pages = {41--48},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/FPT.2004.1393249},
doi = {10.1109/FPT.2004.1393249},
timestamp = {Fri, 22 Nov 2019 15:44:53 +0100},
biburl = {https://dblp.org/rec/conf/fpt/Lemieux0TY04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LemieuxL02,
author = {Guy G. Lemieux and
David M. Lewis},
editor = {Martine D. F. Schlag and
Steve Trimberger},
title = {Circuit design of routing switches},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2002, Monterey, CA, USA, February 24-26, 2002},
pages = {19--28},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/503048.503052},
doi = {10.1145/503048.503052},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LemieuxL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/LemieuxL02,
author = {Guy G. Lemieux and
David M. Lewis},
editor = {Manfred Glesner and
Peter Zipf and
Michel Renovell},
title = {Analytical Framework for Switch Block Design},
booktitle = {Field-Programmable Logic and Applications, Reconfigurable Computing
Is Going Mainstream, 12th International Conference, {FPL} 2002, Montpellier,
France, September 2-4, 2002, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2438},
pages = {122--131},
publisher = {Springer},
year = {2002},
url = {https://doi.org/10.1007/3-540-46117-5\_14},
doi = {10.1007/3-540-46117-5\_14},
timestamp = {Sat, 30 Sep 2023 09:41:27 +0200},
biburl = {https://dblp.org/rec/conf/fpl/LemieuxL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LemieuxL01,
author = {Guy G. Lemieux and
David M. Lewis},
editor = {Scott Hauck and
Martine D. F. Schlag and
Russell Tessier},
title = {Using sparse crossbars within {LUT}},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
pages = {59--68},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/360276.360299},
doi = {10.1145/360276.360299},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LemieuxL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LemieuxLL00,
author = {Guy G. Lemieux and
Paul Leventis and
David M. Lewis},
editor = {Steve Trimberger and
Scott Hauck},
title = {Generating highly-routable sparse crossbars for PLDs},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2000, Monterey, CA, USA, February 10-11, 2000},
pages = {155--164},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/329166.329199},
doi = {10.1145/329166.329199},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LemieuxLL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/GrindleyABCDGGGHKLLMMSSVZ00,
author = {R. Grindley and
Tarek S. Abdelrahman and
Stephen Dean Brown and
S. Caranci and
D. DeVries and
Benjamin Gamsa and
A. Grbic and
M. Gusat and
R. Ho and
Orran Krieger and
Guy G. Lemieux and
K. Loveless and
Naraig Manjikian and
P. McHardy and
Sinisa Srbljic and
Michael Stumm and
Zvonko G. Vranesic and
Zeljko Zilic},
title = {The NUMAchine Multiprocessor},
booktitle = {Proceedings of the 2000 International Conference on Parallel Processing,
{ICPP} 2000, Toronto, Canada, August 21-24, 2000},
pages = {487--496},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICPP.2000.876165},
doi = {10.1109/ICPP.2000.876165},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/GrindleyABCDGGGHKLLMMSSVZ00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/GrbicBCGGLLMSSVZ98,
author = {A. Grbic and
Stephen Dean Brown and
S. Caranci and
R. Grindley and
M. Gusat and
Guy G. Lemieux and
K. Loveless and
Naraig Manjikian and
Sinisa Srbljic and
Michael Stumm and
Zvonko G. Vranesic and
Zeljko Zilic},
editor = {Basant R. Chawla and
Randal E. Bryant and
Jan M. Rabaey},
title = {Design and Implementation of the NUMAchine Multiprocessor},
booktitle = {Proceedings of the 35th Conference on Design Automation, Moscone center,
San Francico, California, USA, June 15-19, 1998},
pages = {66--69},
publisher = {{ACM} Press},
year = {1998},
url = {https://doi.org/10.1145/277044.277057},
doi = {10.1145/277044.277057},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/GrbicBCGGLLMSSVZ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/LemieuxBV97,
author = {Guy G. Lemieux and
Stephen Dean Brown and
Daniel Vranesic},
editor = {Andrew B. Kahng and
Majid Sarrafzadeh},
title = {On two-step routing for {FPGAS}},
booktitle = {Proceedings of the 1997 International Symposium on Physical Design,
{ISPD} 1997, Napa Valley, California, USA, April 14-16, 1997},
pages = {60--66},
publisher = {{ACM}},
year = {1997},
url = {https://doi.org/10.1145/267665.267682},
doi = {10.1145/267665.267682},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/LemieuxBV97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/BrownKL96,
author = {Stephen Dean Brown and
Muhammad M. Khellah and
Guy Lemieux},
title = {Segmented Routing for Speed-Performance and Routability in Field-Programmable
Gate Arrays},
journal = {{VLSI} Design},
volume = {4},
number = {4},
pages = {275--291},
year = {1996},
url = {https://doi.org/10.1155/1996/45983},
doi = {10.1155/1996/45983},
timestamp = {Tue, 06 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/BrownKL96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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