Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBibTeX records: Preeti Ranjan Panda
@article{DBLP:journals/tecs/BagchiJP24,
author = {Aritra Bagchi and
Dinesh Joshi and
Preeti Ranjan Panda},
title = {{COBRRA:} COntention-aware cache Bypass with Request-Response Arbitration},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {23},
number = {1},
pages = {12:1--12:30},
year = {2024},
url = {https://doi.org/10.1145/3632748},
doi = {10.1145/3632748},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tecs/BagchiJP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PandeySP24,
author = {Shailja Pandey and
Lokesh Siddhu and
Preeti Ranjan Panda},
title = {NeuroCool: Dynamic Thermal Management of 3D {DRAM} for Deep Neural
Networks through Customized Prefetching},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {29},
number = {1},
pages = {19:1--19:35},
year = {2024},
url = {https://doi.org/10.1145/3630012},
doi = {10.1145/3630012},
timestamp = {Sat, 10 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/PandeySP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/Panda23,
author = {Preeti Ranjan Panda},
title = {Editorial},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {15},
number = {4},
pages = {169},
year = {2023},
url = {https://doi.org/10.1109/LES.2023.3327351},
doi = {10.1109/LES.2023.3327351},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/esl/Panda23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/ModiBJMP23,
author = {Garima Modi and
Aritra Bagchi and
Neetu Jindal and
Ayan Mandal and
Preeti Ranjan Panda},
title = {{CABARRE:} Request Response Arbitration for Shared Cache Management},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {22},
number = {5s},
pages = {130:1--130:24},
year = {2023},
url = {https://doi.org/10.1145/3608096},
doi = {10.1145/3608096},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/ModiBJMP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/SiddhuBKAPP23,
author = {Lokesh Siddhu and
Aritra Bagchi and
Rajesh Kedia and
Isaar Ahmad and
Shailja Pandey and
Preeti Ranjan Panda},
title = {Dynamic Thermal Management of 3D Memory through Rotating Low Power
States and Partial Channel Closure},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {22},
number = {6},
pages = {104:1--104:27},
year = {2023},
url = {https://doi.org/10.1145/3624581},
doi = {10.1145/3624581},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tecs/SiddhuBKAPP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RavipatiSSAP23,
author = {Divya Praneetha Ravipati and
Victor M. van Santen and
Sami Salamin and
Hussam Amrouch and
Preeti Ranjan Panda},
title = {Performance and Energy Studies on NC-FinFET Cache-Based Systems With
FN-McPAT},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1280--1293},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3285105},
doi = {10.1109/TVLSI.2023.3285105},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RavipatiSSAP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codesisss/PandaP23,
author = {Preeti Ranjan Panda and
Shailja Pandey},
title = {Education Abstract: Thermal Challenges and Mitigation in 3D {DRAM}},
booktitle = {International Conference on Hardware/Software Codesign and System
Synthesis, {CODES+ISSS} 2023, Hamburg, Germany, September 17-22, 2023},
pages = {40--41},
publisher = {{IEEE}},
year = {2023},
url = {https://ieeexplore.ieee.org/document/10317834},
timestamp = {Tue, 05 Dec 2023 20:47:36 +0100},
biburl = {https://dblp.org/rec/conf/codesisss/PandaP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/Panda22,
author = {Preeti Ranjan Panda},
title = {Editorial},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {14},
number = {1},
pages = {1--2},
year = {2022},
url = {https://doi.org/10.1109/LES.2022.3149849},
doi = {10.1109/LES.2022.3149849},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/Panda22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/SiddhuKPRPHP22,
author = {Lokesh Siddhu and
Rajesh Kedia and
Shailja Pandey and
Martin Rapp and
Anuj Pathania and
J{\"{o}}rg Henkel and
Preeti Ranjan Panda},
title = {CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D,
2.5D, and 3D Processor-Memory Systems},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {19},
number = {3},
pages = {44:1--44:25},
year = {2022},
url = {https://doi.org/10.1145/3532185},
doi = {10.1145/3532185},
timestamp = {Mon, 26 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/SiddhuKPRPHP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PandeyP22,
author = {Shailja Pandey and
Preeti Ranjan Panda},
title = {NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic
Thermal Management in High-Bandwidth Memory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {11},
pages = {3602--3613},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2022.3197698},
doi = {10.1109/TCAD.2022.3197698},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/PandeyP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RavipatiKSHPA22,
author = {Divya Praneetha Ravipati and
Rajesh Kedia and
Victor M. van Santen and
J{\"{o}}rg Henkel and
Preeti Ranjan Panda and
Hussam Amrouch},
title = {{FN-CACTI:} Advanced {CACTI} for FinFET and NC-FinFET Technologies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {3},
pages = {339--352},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3123112},
doi = {10.1109/TVLSI.2021.3123112},
timestamp = {Wed, 27 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RavipatiKSHPA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SiddhuKP22,
author = {Lokesh Siddhu and
Rajesh Kedia and
Preeti Ranjan Panda},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal
Management for Improved Performance},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {1377--1382},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774743},
doi = {10.23919/DATE54114.2022.9774743},
timestamp = {Wed, 25 May 2022 22:56:19 +0200},
biburl = {https://dblp.org/rec/conf/date/SiddhuKP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/csur/BraisKP20,
author = {Hadi Brais and
Rajshekar Kalayappan and
Preeti Ranjan Panda},
title = {A Survey of Cache Simulators},
journal = {{ACM} Comput. Surv.},
volume = {53},
number = {1},
pages = {19:1--19:32},
year = {2021},
url = {https://doi.org/10.1145/3372393},
doi = {10.1145/3372393},
timestamp = {Wed, 23 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/csur/BraisKP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SiddhuKP20,
author = {Lokesh Siddhu and
Rajesh Kedia and
Preeti Ranjan Panda},
title = {Leakage-Aware Dynamic Thermal Management of 3D Memories},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {26},
number = {2},
pages = {12:1--12:31},
year = {2021},
url = {https://doi.org/10.1145/3419468},
doi = {10.1145/3419468},
timestamp = {Tue, 16 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/SiddhuKP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/cases/2021,
editor = {{\"{U}}mit Y. Ogras and
Preeti Ranjan Panda},
title = {{CASES} '21: Proceedings of the 2021 International Conference on Compilers,
Architectures, and Synthesis for Embedded Systems, Virtual Event,
October 8 - 15, 2021},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3451939},
doi = {10.1145/3451939},
isbn = {978-1-4503-8378-3},
timestamp = {Thu, 09 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/2021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2109-12405,
author = {Lokesh Siddhu and
Rajesh Kedia and
Shailja Pandey and
Martin Rapp and
Anuj Pathania and
J{\"{o}}rg Henkel and
Preeti Ranjan Panda},
title = {CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D,
2.5D, and 3D Processor-Memory Systems},
journal = {CoRR},
volume = {abs/2109.12405},
year = {2021},
url = {https://arxiv.org/abs/2109.12405},
eprinttype = {arXiv},
eprint = {2109.12405},
timestamp = {Mon, 04 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2109-12405.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/Panda20,
author = {Preeti Ranjan Panda},
title = {Editorial-December 2020},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {12},
number = {4},
pages = {103--104},
year = {2020},
url = {https://doi.org/10.1109/LES.2020.3007539},
doi = {10.1109/LES.2020.3007539},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/Panda20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JindalGRPS20,
author = {Neetu Jindal and
Shubhani Gupta and
Divya Praneetha Ravipati and
Preeti Ranjan Panda and
Smruti R. Sarangi},
title = {Enhancing Network-on-Chip Performance by Reusing Trace Buffers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {4},
pages = {922--935},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2907909},
doi = {10.1109/TCAD.2019.2907909},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JindalGRPS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/TiwariTAAPS20,
author = {Sakshi Tiwari and
Shreshth Tuli and
Isaar Ahmad and
Ayushi Agarwal and
Preeti Ranjan Panda and
Sreenivas Subramoney},
title = {{REAL:} REquest Arbitration in Last Level Caches},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {18},
number = {6},
pages = {115:1--115:24},
year = {2020},
url = {https://doi.org/10.1145/3362100},
doi = {10.1145/3362100},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tecs/TiwariTAAPS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/SiddhuP19,
author = {Lokesh Siddhu and
Preeti Ranjan Panda},
title = {PredictNcool: Leakage Aware Thermal Management for 3D Memories Using
a Lightweight Temperature Predictor},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {18},
number = {5s},
pages = {64:1--64:22},
year = {2019},
url = {https://doi.org/10.1145/3358208},
doi = {10.1145/3358208},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/SiddhuP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/BraisP19,
author = {Hadi Brais and
Preeti Ranjan Panda},
title = {Alleria: An Advanced Memory Access Profiling Framework},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {18},
number = {5s},
pages = {81:1--81:22},
year = {2019},
url = {https://doi.org/10.1145/3358193},
doi = {10.1145/3358193},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/BraisP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/JindalCPPMSGT19,
author = {Neetu Jindal and
Sandeep Chandran and
Preeti Ranjan Panda and
Sanjiva Prasad and
Abhay Mitra and
Kunal Singhal and
Shubham Gupta and
Shikhar Tuli},
title = {{DHOOM:} Reusing Design-for-Debug Hardware for Online Monitoring},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {99},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3317799},
doi = {10.1145/3316781.3317799},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/JindalCPPMSGT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SiddhuP19,
author = {Lokesh Siddhu and
Preeti Ranjan Panda},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {272--275},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8715091},
doi = {10.23919/DATE.2019.8715091},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/SiddhuP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/MenonGPKTMRKPP19,
author = {Sankaran M. Menon and
Ashish Gupta and
Chinna Prudvi and
Rolf K{\"{u}}hnis and
Sukhbinder Singh Takhar and
Spencer K. Millican and
Eric Rentschler and
Pandy Kalimuthu and
Preeti Ranjan Panda and
Priyadarsan Patra},
title = {Techniques for Debug of Low Power SoCs},
booktitle = {20th International Workshop on Microprocessor/SoC Test, Security and
Verification, {MTV} 2019, Austin, TX, USA, December 9-10, 2019},
pages = {45--49},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/MTV48867.2019.00017},
doi = {10.1109/MTV48867.2019.00017},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtv/MenonGPKTMRKPP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ParmarMPS19,
author = {Vivek Kamalkant Parmar and
Swatilekha Majumdar and
Preeti Ranjan Panda and
Manan Suri},
title = {Investigation of Unified Emerging-NVM SoC Architecture for IoT-WSN
Applications},
booktitle = {32nd International Conference on {VLSI} Design and 18th International
Conference on Embedded Systems, {VLSID} 2019, Delhi, India, January
5-9, 2019},
pages = {281--286},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSID.2019.00067},
doi = {10.1109/VLSID.2019.00067},
timestamp = {Mon, 14 Nov 2022 15:28:06 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/ParmarMPS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JindalPS18,
author = {Neetu Jindal and
Preeti Ranjan Panda and
Smruti R. Sarangi},
title = {Reusing Trace Buffers as Victim Caches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {9},
pages = {1699--1712},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2827928},
doi = {10.1109/TVLSI.2018.2827928},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JindalPS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/Panda0KBS18,
author = {Preeti Ranjan Panda and
Namita Sharma and
Srikanth Kurra and
Khushboo Anil Bhartia and
Neeraj Kumar Singh},
title = {Exploration of Loop Unroll Factors in High Level Synthesis},
booktitle = {31st International Conference on {VLSI} Design and 17th International
Conference on Embedded Systems, {VLSID} 2018, Pune, India, January
6-10, 2018},
pages = {465--466},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/VLSID.2018.115},
doi = {10.1109/VLSID.2018.115},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/Panda0KBS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/JainPS17,
author = {Rahul Jain and
Preeti Ranjan Panda and
Sreenivas Subramoney},
title = {Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization
of Cores, Caches, and On-chip Network},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {14},
number = {4},
pages = {32:1--32:25},
year = {2017},
url = {https://doi.org/10.1145/3132170},
doi = {10.1145/3132170},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/JainPS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChandranPSBCK17,
author = {Sandeep Chandran and
Preeti Ranjan Panda and
Smruti R. Sarangi and
Ayan Bhattacharyya and
Deepak Chauhan and
Sharad Kumar},
title = {Managing Trace Summaries to Minimize Stalls During Postsilicon Validation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1881--1894},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2657604},
doi = {10.1109/TVLSI.2017.2657604},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChandranPSBCK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/JindalPS17,
author = {Neetu Jindal and
Preeti Ranjan Panda and
Smruti R. Sarangi},
editor = {David Atienza and
Giorgio Di Natale},
title = {Reusing trace buffers to enhance cache performance},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {572--577},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927052},
doi = {10.23919/DATE.2017.7927052},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/JindalPS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/0004PS17,
author = {Rahul Jain and
Preeti Ranjan Panda and
Sreenivas Subramoney},
editor = {David Atienza and
Giorgio Di Natale},
title = {A coordinated multi-agent reinforcement learning approach to multi-level
cache co-partitioning},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {800--805},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927098},
doi = {10.23919/DATE.2017.7927098},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/0004PS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/hwswco/Panda17,
author = {Preeti Ranjan Panda},
editor = {Soonhoi Ha and
J{\"{u}}rgen Teich},
title = {Memory Architectures},
booktitle = {Handbook of Hardware/Software Codesign},
pages = {411--441},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-94-017-7267-9\_14},
doi = {10.1007/978-94-017-7267-9\_14},
timestamp = {Tue, 06 Aug 2019 10:05:03 +0200},
biburl = {https://dblp.org/rec/reference/hwswco/Panda17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/0001PCLA16,
author = {Namita Sharma and
Preeti Ranjan Panda and
Francky Catthoor and
Min Li and
Prashant Agrawal},
title = {Data Flow Transformation for Energy-Efficient Implementation of Givens
Rotation-Based {QRD}},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {15},
number = {1},
pages = {18:1--18:23},
year = {2016},
url = {https://doi.org/10.1145/2837025},
doi = {10.1145/2837025},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/0001PCLA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/FilippopoulosSC16,
author = {Iason Filippopoulos and
Namita Sharma and
Francky Catthoor and
Per Gunnar Kjeldsberg and
Preeti Ranjan Panda},
title = {Integrated Exploration Methodology for Data Interleaving and Data-to-Memory
Mapping on {SIMD} Architectures},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {15},
number = {3},
pages = {59:1--59:23},
year = {2016},
url = {https://doi.org/10.1145/2894754},
doi = {10.1145/2894754},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/FilippopoulosSC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ChakrabortyPS16,
author = {Prasenjit Chakraborty and
Preeti Ranjan Panda and
Sandeep Sen},
title = {Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad
Memory-Based Architectures},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {22},
number = {1},
pages = {12:1--12:25},
year = {2016},
url = {https://doi.org/10.1145/2934680},
doi = {10.1145/2934680},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/ChakrabortyPS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChandranSP16,
author = {Sandeep Chandran and
Smruti R. Sarangi and
Preeti Ranjan Panda},
title = {Area-Aware Cache Update Trackers for Postsilicon Validation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {5},
pages = {1794--1807},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2480378},
doi = {10.1109/TVLSI.2015.2480378},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChandranSP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChandranPCKS16,
author = {Sandeep Chandran and
Preeti Ranjan Panda and
Deepak Chauhan and
Sharad Kumar and
Smruti R. Sarangi},
title = {Extending trace history through tapered summaries in post-silicon
validation},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {737--742},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7428099},
doi = {10.1109/ASPDAC.2016.7428099},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChandranPCKS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/JainPS16,
author = {Rahul Jain and
Preeti Ranjan Panda and
Sreenivas Subramoney},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {Machine Learned Machines: Adaptive co-optimization of caches, cores,
and On-chip Network},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {253--256},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459315/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/JainPS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ChandranPPS16,
author = {Sandeep Chandran and
Eldhose Peter and
Preeti Ranjan Panda and
Smruti R. Sarangi},
title = {A Generic Implementation of Barriers Using Optical Interconnects},
booktitle = {29th International Conference on {VLSI} Design and 15th International
Conference on Embedded Systems, {VLSID} 2016, Kolkata, India, January
4-8, 2016},
pages = {349--354},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/VLSID.2016.16},
doi = {10.1109/VLSID.2016.16},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/ChandranPPS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SharmaPCRA15,
author = {Namita Sharma and
Preeti Ranjan Panda and
Francky Catthoor and
Praveen Raghavan and
Tom Vander Aa},
title = {Array Interleaving - An Energy-Efficient Data Layout Transformation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {20},
number = {3},
pages = {44:1--44:26},
year = {2015},
url = {https://doi.org/10.1145/2747875},
doi = {10.1145/2747875},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/SharmaPCRA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/SharmaPC15,
author = {Namita Sharma and
Preeti Ranjan Panda and
Francky Catthoor},
editor = {Gabriela Nicolescu and
Andreas Gerstlauer},
title = {Energy efficient {FFT} implementation through stage skipping and merging},
booktitle = {2015 International Conference on Hardware/Software Codesign and System
Synthesis, {CODES+ISSS} 2015, Amsterdam, Netherlands, October 4-9,
2015},
pages = {153--162},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/CODESISSS.2015.7331378},
doi = {10.1109/CODESISSS.2015.7331378},
timestamp = {Wed, 16 Oct 2019 14:14:48 +0200},
biburl = {https://dblp.org/rec/conf/codes/SharmaPC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PandaPSSSS15,
author = {Preeti Ranjan Panda and
Vishal Patel and
Praxal Shah and
Namita Sharma and
Vaidyanathan Srinivasan and
Dipankar Sarma},
title = {Power Optimization Techniques for {DDR3} {SDRAM}},
booktitle = {28th International Conference on {VLSI} Design, {VLSID} 2015, Bangalore,
India, January 3-7, 2015},
pages = {310--315},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/VLSID.2015.59},
doi = {10.1109/VLSID.2015.59},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PandaPSSSS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/ChandranPPS15,
author = {Sandeep Chandran and
Eldhose Peter and
Preeti Ranjan Panda and
Smruti R. Sarangi},
title = {Fundamental Results for a Generic Implementation of Barriers using
Optical Interconnects},
journal = {CoRR},
volume = {abs/1510.00220},
year = {2015},
url = {http://arxiv.org/abs/1510.00220},
eprinttype = {arXiv},
eprint = {1510.00220},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/ChandranPPS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/GoelKP14,
author = {Neeraj Goel and
Anshul Kumar and
Preeti Ranjan Panda},
title = {Shared-port register file architecture for low-energy {VLIW} processors},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {11},
number = {1},
pages = {1:1--1:32},
year = {2014},
url = {https://doi.org/10.1145/2533397},
doi = {10.1145/2533397},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/GoelKP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/PandaSPKSJ14,
author = {Preeti Ranjan Panda and
Namita Sharma and
Arun Kumar Pilania and
Gummidipudi Krishnaiah and
Sreenivas Subramoney and
Ashok Jagannathan},
title = {Array scalarization in high level synthesis},
booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2014, Singapore, January 20-23, 2014},
pages = {622--627},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASPDAC.2014.6742960},
doi = {10.1109/ASPDAC.2014.6742960},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/PandaSPKSJ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/AlamPTSN14,
author = {Faisal Alam and
Preeti Ranjan Panda and
Nikhil Tripathi and
Namita Sharma and
Sanjiv Narayan},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Energy optimization in Android applications through wakelock placement},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--4},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.101},
doi = {10.7873/DATE.2014.101},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/AlamPTSN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SharmaPLAC14,
author = {Namita Sharma and
Preeti Ranjan Panda and
Min Li and
Prashant Agrawal and
Francky Catthoor},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Energy efficient data flow transformation for Givens Rotation based
{QR} Decomposition},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--4},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.224},
doi = {10.7873/DATE.2014.224},
timestamp = {Thu, 28 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/SharmaPLAC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PandaRCSKKN14,
author = {Preeti Ranjan Panda and
Sourav Roy and
Srikanth Chandrasekaran and
Namita Sharma and
Jasleen Kaur and
Sarath Kumar Kandalam and
Nagaraj N.},
editor = {Joseph R. Cavallaro and
Tong Zhang and
Alex K. Jones and
Hai (Helen) Li},
title = {High level energy modeling of controller logic in data caches},
booktitle = {Great Lakes Symposium on {VLSI} 2014, {GLSVLSI} '14, Houston, TX,
{USA} - May 21 - 23, 2014},
pages = {45--50},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2591513.2591590},
doi = {10.1145/2591513.2591590},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PandaRCSKKN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/ChakrabortyP13,
author = {Prasenjit Chakraborty and
Preeti Ranjan Panda},
title = {SPM-Sieve: {A} framework for assisting data partitioning in scratch
pad memory based systems},
booktitle = {International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2013, Montreal, QC, Canada, September
29 - October 4, 2013},
pages = {21:1--21:10},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CASES.2013.6662527},
doi = {10.1109/CASES.2013.6662527},
timestamp = {Wed, 16 Oct 2019 14:14:51 +0200},
biburl = {https://dblp.org/rec/conf/cases/ChakrabortyP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/MarculescuP13,
author = {Radu Marculescu and
Preeti Ranjan Panda},
title = {Message from the program co-chairs},
booktitle = {Proceedings of the International Conference on Hardware/Software Codesign
and System Synthesis, {CODES+ISSS} 2013, Montreal, QC, Canada, September
29 - October 4, 2013},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CODES-ISSS.2013.6658984},
doi = {10.1109/CODES-ISSS.2013.6658984},
timestamp = {Wed, 16 Oct 2019 14:14:48 +0200},
biburl = {https://dblp.org/rec/conf/codes/MarculescuP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChandranSP13,
author = {Sandeep Chandran and
Smruti R. Sarangi and
Preeti Ranjan Panda},
editor = {Enrico Macii},
title = {Space sensitive cache dumping for post-silicon validation},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {497--502},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.113},
doi = {10.7873/DATE.2013.113},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/ChandranSP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/SharmaAARPC13,
author = {Namita Sharma and
Tom Vander Aa and
Prashant Agrawal and
Praveen Raghavan and
Preeti Ranjan Panda and
Francky Catthoor},
title = {Data memory optimization in {LTE} downlink},
booktitle = {{IEEE} International Conference on Acoustics, Speech and Signal Processing,
{ICASSP} 2013, Vancouver, BC, Canada, May 26-31, 2013},
pages = {2610--2614},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ICASSP.2013.6638128},
doi = {10.1109/ICASSP.2013.6638128},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/icassp/SharmaAARPC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PandaJVSS13,
author = {Preeti Ranjan Panda and
Manoj Jain and
Anubha Verma and
Dipankar Sarma and
Vaidyanathan Srinivasan},
title = {Power Supply Efficiency Aware Server Allocation in Data Centers},
booktitle = {26th International Conference on {VLSI} Design and 12th International
Conference on Embedded Systems, Pune, India, January 5-10, 2013},
pages = {233--238},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/VLSID.2013.193},
doi = {10.1109/VLSID.2013.193},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PandaJVSS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/JainKP12,
author = {Vaibhav Jain and
Anshul Kumar and
Preeti Ranjan Panda},
title = {Exploiting {UML} based validation for compliance checking of {TLM}
2 based models},
journal = {Des. Autom. Embed. Syst.},
volume = {16},
number = {2},
pages = {93--113},
year = {2012},
url = {https://doi.org/10.1007/s10617-012-9089-7},
doi = {10.1007/S10617-012-9089-7},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dafes/JainKP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/ChakrabortyP12,
author = {Prasenjit Chakraborty and
Preeti Ranjan Panda},
editor = {Ahmed Jerraya and
Luca P. Carloni and
Vincent John Mooney III and
Rodric M. Rabbah},
title = {Integrating software caches with scratch pad memory},
booktitle = {Proceedings of the 15th International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems, {CASES} 2012, part of the Eighth
Embedded Systems Week, ESWeek 2012, Tampere, Finland, October 7-12,
2012},
pages = {201--210},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2380403.2380440},
doi = {10.1145/2380403.2380440},
timestamp = {Thu, 11 Mar 2021 17:04:51 +0100},
biburl = {https://dblp.org/rec/conf/cases/ChakrabortyP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fsttcs/KumarPS12,
author = {Amit Kumar and
Preeti Ranjan Panda and
Smruti R. Sarangi},
editor = {Deepak D'Souza and
Telikepalli Kavitha and
Jaikumar Radhakrishnan},
title = {Efficient on-line algorithm for maintaining k-cover of sparse bit-strings},
booktitle = {{IARCS} Annual Conference on Foundations of Software Technology and
Theoretical Computer Science, {FSTTCS} 2012, December 15-17, 2012,
Hyderabad, India},
series = {LIPIcs},
volume = {18},
pages = {249--256},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2012},
url = {https://doi.org/10.4230/LIPIcs.FSTTCS.2012.249},
doi = {10.4230/LIPICS.FSTTCS.2012.249},
timestamp = {Thu, 12 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fsttcs/KumarPS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PandaBV11,
author = {Preeti Ranjan Panda and
M. Balakrishnan and
Anant Vishnoi},
title = {Compressing Cache State for Postsilicon Processor Debug},
journal = {{IEEE} Trans. Computers},
volume = {60},
number = {4},
pages = {484--497},
year = {2011},
url = {https://doi.org/10.1109/TC.2010.123},
doi = {10.1109/TC.2010.123},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PandaBV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/KrishnaiahSPK11,
author = {Gummidipudi Krishnaiah and
B. V. N. Silpa and
Preeti Ranjan Panda and
Anshul Kumar},
editor = {Robert P. Dick and
Jan Madsen},
title = {Exploiting temporal decoupling to accelerate trace-driven NoC emulation},
booktitle = {Proceedings of the 9th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2011, part of ESWeek '11
Seventh Embedded Systems Week, Taipei, Taiwan, 9-14 October, 2011},
pages = {315--324},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2039370.2039418},
doi = {10.1145/2039370.2039418},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/KrishnaiahSPK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ecmdafa/JainKP11,
author = {Vaibhav Jain and
Anshul Kumar and
Preeti Ranjan Panda},
editor = {Robert B. France and
Jochen Malte K{\"{u}}ster and
Behzad Bordbar and
Richard F. Paige},
title = {A SysML Profile for Development and Early Validation of {TLM} 2.0
Models},
booktitle = {Modelling Foundations and Applications - 7th European Conference,
{ECMFA} 2011, Birmingham, UK, June 6 - 9, 2011 Proceedings},
series = {Lecture Notes in Computer Science},
volume = {6698},
pages = {299--311},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-21470-7\_21},
doi = {10.1007/978-3-642-21470-7\_21},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ecmdafa/JainKP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/JainKP11,
author = {Vaibhav Jain and
Anshul Kumar and
Preeti Ranjan Panda},
title = {A {UML} based framework for efficient validation of {TLM} 2 models},
booktitle = {2011 Forum on Specification {\&} Design Languages, {FDL} 2011,
Oldenburg, Germany, September 13-15, 2011},
pages = {1--8},
publisher = {{IEEE}},
year = {2011},
url = {https://ieeexplore.ieee.org/document/6069478/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/JainKP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/PandaP10,
author = {Preeti Ranjan Panda and
Rajendran Panda},
title = {Guest Editorial: Special Issue on {VLSI} Design and Embedded Systems},
journal = {Int. J. Parallel Program.},
volume = {38},
number = {3-4},
pages = {183--184},
year = {2010},
url = {https://doi.org/10.1007/s10766-010-0133-6},
doi = {10.1007/S10766-010-0133-6},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijpp/PandaP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/SilpaKP10,
author = {B. V. N. Silpa and
Gummidipudi Krishnaiah and
Preeti Ranjan Panda},
editor = {Tony Givargis and
Adam Donlin},
title = {Rank based dynamic voltage and frequency scaling fortiled graphics
processors},
booktitle = {Proceedings of the 8th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2010, part of ESWeek '10
Sixth Embedded Systems Week, Scottsdale, AZ, USA, October 24-28, 2010},
pages = {3--12},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1878961.1878965},
doi = {10.1145/1878961.1878965},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/SilpaKP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/KrishnaiahSPK10,
author = {Gummidipudi Krishnaiah and
B. V. N. Silpa and
Preeti Ranjan Panda and
Anshul Kumar},
editor = {Tony Givargis and
Adam Donlin},
title = {FastFwd: an efficient hardware acceleration technique for trace-driven
network-on-chip simulation},
booktitle = {Proceedings of the 8th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2010, part of ESWeek '10
Sixth Embedded Systems Week, Scottsdale, AZ, USA, October 24-28, 2010},
pages = {247--256},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1878961.1879006},
doi = {10.1145/1878961.1879006},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codes/KrishnaiahSPK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PandaVB10,
author = {Preeti Ranjan Panda and
Anant Vishnoi and
M. Balakrishnan},
title = {Enhancing post-silicon processor debug with Incremental Cache state
Dumping},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {55--60},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642623},
doi = {10.1109/VLSISOC.2010.5642623},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PandaVB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KumarP10,
author = {Anshul Kumar and
Preeti Ranjan Panda},
title = {Front-End Design Flows for Systems on Chip: An Embedded Tutorial},
booktitle = {{VLSI} Design 2010: 23rd International Conference on {VLSI} Design,
9th International Conference on Embedded Systems, Bangalore, India,
3-7 January 2010},
pages = {417--422},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VLSI.Design.2010.70},
doi = {10.1109/VLSI.DESIGN.2010.70},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/KumarP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/PandaP09,
author = {Rajendran Panda and
Preeti Ranjan Panda},
title = {\emph{A Special Issue on the} "22nd {IEEE} International Conference
on {VLSI} Design" New Delhi, India, 5-9 January 2009},
journal = {J. Low Power Electron.},
volume = {5},
number = {3},
pages = {255--256},
year = {2009},
url = {https://doi.org/10.1166/jolpe.2009.1026},
doi = {10.1166/JOLPE.2009.1026},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/PandaP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/VishnoiPB09,
author = {Anant Vishnoi and
Preeti Ranjan Panda and
M. Balakrishnan},
title = {Online cache state dumping for processor debug},
booktitle = {Proceedings of the 46th Design Automation Conference, {DAC} 2009,
San Francisco, CA, USA, July 26-31, 2009},
pages = {358--363},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629911.1630007},
doi = {10.1145/1629911.1630007},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/VishnoiPB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/VishnoiPB09,
author = {Anant Vishnoi and
Preeti Ranjan Panda and
M. Balakrishnan},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {Cache aware compression for processor debug support},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {208--213},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090659},
doi = {10.1109/DATE.2009.5090659},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/VishnoiPB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SahuBP09,
author = {Aryabartta Sahu and
M. Balakrishnan and
Preeti Ranjan Panda},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {A generic platform for estimation of multi-threaded program performance
on heterogeneous multiprocessors},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {1018--1023},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090813},
doi = {10.1109/DATE.2009.5090813},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/SahuBP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvc/SilpaVP09,
author = {B. V. N. Silpa and
Kumar S. S. Vemuri and
Preeti Ranjan Panda},
editor = {George Bebis and
Richard D. Boyle and
Bahram Parvin and
Darko Koracin and
Yoshinori Kuno and
Junxian Wang and
Renato Pajarola and
Peter Lindstrom and
Andr{\'{e}} Hinkenjann and
L. Miguel Encarna{\c{c}}{\~{a}}o and
Cl{\'{a}}udio T. Silva and
Daniel S. Coming},
title = {Adaptive Partitioning of Vertex Shader for Low Power High Performance
Geometry Engine},
booktitle = {Advances in Visual Computing, 5th International Symposium, {ISVC}
2009, Las Vegas, NV, USA, November 30 - December 2, 2009, Proceedings,
Part {I}},
series = {Lecture Notes in Computer Science},
volume = {5875},
pages = {111--124},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-642-10331-5\_11},
doi = {10.1007/978-3-642-10331-5\_11},
timestamp = {Wed, 04 May 2022 07:33:36 +0200},
biburl = {https://dblp.org/rec/conf/isvc/SilpaVP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/Panda08,
author = {Preeti Ranjan Panda},
title = {Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded
Systems},
journal = {Int. J. Parallel Program.},
volume = {36},
number = {1},
pages = {1--2},
year = {2008},
url = {https://doi.org/10.1007/s10766-007-0060-3},
doi = {10.1007/S10766-007-0060-3},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijpp/Panda08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/TripathiJKP08,
author = {Pushkar Tripathi and
Rohan Jain and
Srikanth Kurra and
Preeti Ranjan Panda},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {{REWIRED} - Register Write Inhibition by Resource Dedication},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {28--31},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4483960},
doi = {10.1109/ASPDAC.2008.4483960},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/TripathiJKP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SilpaPKPV08,
author = {B. V. N. Silpa and
Anjul Patney and
Tushar Krishna and
Preeti Ranjan Panda and
G. S. Visweswaran},
editor = {Sani R. Nassif and
Jaijeet S. Roychowdhury},
title = {Texture filter memory: a power-efficient and scalable texture memory
architecture for mobile graphics processors},
booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008,
San Jose, CA, USA, November 10-13, 2008},
pages = {559--564},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCAD.2008.4681631},
doi = {10.1109/ICCAD.2008.4681631},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SilpaPKPV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/GangwarBPK07,
author = {Anup Gangwar and
M. Balakrishnan and
Preeti Ranjan Panda and
Anshul Kumar},
title = {Evaluation of Bus Based Interconnect Mechanisms in Clustered {VLIW}
Architectures},
journal = {Int. J. Parallel Program.},
volume = {35},
number = {6},
pages = {507--527},
year = {2007},
url = {https://doi.org/10.1007/s10766-007-0045-2},
doi = {10.1007/S10766-007-0045-2},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijpp/GangwarBPK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KurraSP07,
author = {Srikanth Kurra and
Neeraj Kumar Singh and
Preeti Ranjan Panda},
editor = {Rudy Lauwereins and
Jan Madsen},
title = {The impact of loop unrolling on controller delay in high level synthesis},
booktitle = {2007 Design, Automation and Test in Europe Conference and Exposition,
{DATE} 2007, Nice, France, April 16-20, 2007},
pages = {391--396},
publisher = {{EDA} Consortium, San Jose, CA, {USA}},
year = {2007},
url = {https://doi.org/10.1109/DATE.2007.364623},
doi = {10.1109/DATE.2007.364623},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/KurraSP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/JainP07,
author = {Rahul Jain and
Preeti Ranjan Panda},
title = {An Efficient Pipelined {VLSI} Architecture for Lifting-Based 2D-Discrete
Wavelet Transform},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {1377--1380},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378484},
doi = {10.1109/ISCAS.2007.378484},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/JainP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GoelKP07,
author = {Neeraj Goel and
Anshul Kumar and
Preeti Ranjan Panda},
title = {Power Reduction in {VLIW} Processor with Compiler Driven Bypass Network},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {233--238},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.127},
doi = {10.1109/VLSID.2007.127},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GoelKP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/NalluriGP07,
author = {Rakesh Nalluri and
Rohan Garg and
Preeti Ranjan Panda},
title = {Customization of Register File Banking Architecture for Low Power},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {239--244},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.58},
doi = {10.1109/VLSID.2007.58},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/NalluriGP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/JainP07,
author = {Rahul Jain and
Preeti Ranjan Panda},
title = {Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet
Transform},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {813--818},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.103},
doi = {10.1109/VLSID.2007.103},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/JainP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Panda06,
author = {Preeti Ranjan Panda},
editor = {Fumiyasu Hirose},
title = {Abridged addressing: a low power memory addressing strategy},
booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation:
{ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006},
pages = {892--897},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ASPDAC.2006.1594799},
doi = {10.1109/ASPDAC.2006.1594799},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/Panda06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/GuptaGP06,
author = {Gagan Raj Gupta and
Madhur Gupta and
Preeti Ranjan Panda},
editor = {Ellen Sentovich},
title = {Rapid estimation of control delay from high-level specifications},
booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006,
San Francisco, CA, USA, July 24-28, 2006},
pages = {455--458},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1146909.1147029},
doi = {10.1145/1146909.1147029},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/GuptaGP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GangwarBPK05,
author = {Anup Gangwar and
M. Balakrishnan and
Preeti Ranjan Panda and
Anshul Kumar},
title = {Evaluation of Bus Based Interconnect Mechanisms in Clustered {VLIW}
Architectures},
booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2005), 7-11 March 2005, Munich, Germany},
pages = {730--735},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DATE.2005.141},
doi = {10.1109/DATE.2005.141},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/GangwarBPK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SaunP05,
author = {Vikram Singh Saun and
Preeti Ranjan Panda},
title = {Extracting Exact Finite State Machines from Behavioral SystemC Descriptions},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {280--285},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.98},
doi = {10.1109/ICVD.2005.98},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SaunP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeoKP03,
author = {Jaewon Seo and
Taewhan Kim and
Preeti Ranjan Panda},
title = {Memory allocation and mapping in high-level synthesis - an integrated
approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {928--938},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817116},
doi = {10.1109/TVLSI.2003.817116},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeoKP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ChandraPHPR03,
author = {Ramesh Chandra and
Preeti Ranjan Panda and
J{\"{o}}rg Henkel and
Sri Parameswaran and
Loganath Ramachandran},
title = {Specification and Design of Multi-Million Gate SOCs},
booktitle = {16th International Conference on {VLSI} Design {(VLSI} Design 2003),
4-8 January 2003, New Delhi, India},
pages = {18--19},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ICVD.2003.1183107},
doi = {10.1109/ICVD.2003.1183107},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/ChandraPHPR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SeoKP02,
author = {Jaewon Seo and
Taewhan Kim and
Preeti Ranjan Panda},
title = {An integrated algorithm for memory allocation and assignment in high-level
synthesis},
booktitle = {Proceedings of the 39th Design Automation Conference, {DAC} 2002,
New Orleans, LA, USA, June 10-14, 2002},
pages = {608--611},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/513918.514072},
doi = {10.1145/513918.514072},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SeoKP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipc/PandaD02a,
author = {Preeti Ranjan Panda and
Nikil D. Dutt},
editor = {Sartaj Sahni and
Viktor K. Prasanna and
Uday Shukla},
title = {Memory Architectures for Embedded Systems-On-Chip},
booktitle = {High Performance Computing - HiPC 2002, 9th International Conference,
Bangalore, India, December 18-21, 2002, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2552},
pages = {647--662},
publisher = {Springer},
year = {2002},
url = {https://doi.org/10.1007/3-540-36265-7\_61},
doi = {10.1007/3-540-36265-7\_61},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hipc/PandaD02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PandaC02,
author = {Preeti Ranjan Panda and
Lakshmikantam Chitturi},
editor = {Lawrence T. Pileggi and
Andreas Kuehlmann},
title = {An energy-conscious algorithm for memory port allocation},
booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided
Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002},
pages = {572--576},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1145/774572.774656},
doi = {10.1145/774572.774656},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PandaC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/PandaDNCVBKG01,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau and
Francky Catthoor and
Arnout Vandecappelle and
Erik Brockmeyer and
Chidamber Kulkarni and
Eddy de Greef},
title = {Data Memory Organization and Optimizations in Application-Specific
Systems},
journal = {{IEEE} Des. Test Comput.},
volume = {18},
number = {3},
pages = {56--68},
year = {2001},
url = {https://doi.org/10.1109/54.922803},
doi = {10.1109/54.922803},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/PandaDNCVBKG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PandaCDDBKVK01,
author = {Preeti Ranjan Panda and
Francky Catthoor and
Nikil D. Dutt and
Koen Danckaert and
Erik Brockmeyer and
Chidamber Kulkarni and
Arnout Vandecappelle and
Per Gunnar Kjeldsberg},
title = {Data and memory optimization techniques for embedded systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {6},
number = {2},
pages = {149--206},
year = {2001},
url = {https://doi.org/10.1145/375977.375978},
doi = {10.1145/375977.375978},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/PandaCDDBKVK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isss/Panda01,
author = {Preeti Ranjan Panda},
editor = {Rom{\'{a}}n Hermida and
El Mostapha Aboulhamid},
title = {SystemC: {A} Modeling Platform Supporting Multiple Design Abstractions},
booktitle = {Proceedings of the 14th International Symposium on Systems Synthesis,
{ISSS} 2001, Montr{\'{e}}l, Qu{\'{e}}bec, Canada, September
30 - October 3, 2001},
pages = {75--80},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ISSS.2001.957916},
doi = {10.1109/ISSS.2001.957916},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isss/Panda01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isss/RosenstielBFGGP01,
author = {Wolfgang Rosenstiel and
Brian Bailey and
Masahiro Fujita and
Guang R. Gao and
Rajesh K. Gupta and
Preeti Ranjan Panda},
editor = {Rom{\'{a}}n Hermida and
El Mostapha Aboulhamid},
title = {New Design Paradigms: What Needs to be Standardized?},
booktitle = {Proceedings of the 14th International Symposium on Systems Synthesis,
{ISSS} 2001, Montr{\'{e}}l, Qu{\'{e}}bec, Canada, September
30 - October 3, 2001},
pages = {94},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2001},
url = {https://doi.ieeecomputersociety.org/10.1109/ISSS.2001.10000},
doi = {10.1109/ISSS.2001.10000},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isss/RosenstielBFGGP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isss/PandaSM01,
author = {Preeti Ranjan Panda and
Luc S{\'{e}}m{\'{e}}ria and
Giovanni De Micheli},
editor = {Rom{\'{a}}n Hermida and
El Mostapha Aboulhamid},
title = {Cache-efficient memory layout of aggregate data structures},
booktitle = {Proceedings of the 14th International Symposium on Systems Synthesis,
{ISSS} 2001, Montr{\'{e}}l, Qu{\'{e}}bec, Canada, September
30 - October 3, 2001},
pages = {101--106},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2001},
url = {https://doi.ieeecomputersociety.org/10.1109/ISSS.2001.957921},
doi = {10.1109/ISSS.2001.957921},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isss/PandaSM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/Keitel-ShulzWCP01,
author = {Doris Keitel{-}Schulz and
Norbert Wehn and
Francky Catthoor and
Preeti Ranjan Panda},
title = {Embedded Memories in System Design: Technology, Application, Design
and Tools},
booktitle = {14th International Conference on {VLSI} Design {(VLSI} Design 2001),
3-7 January 2001, Bangalore, India},
pages = {5--6},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2001.10005},
doi = {10.1109/VLSID.2001.10005},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/Keitel-ShulzWCP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PandaDN00,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau},
title = {On-chip vs. off-chip memory: the data partitioning problem in embedded
processor-based systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {682--704},
year = {2000},
url = {https://doi.org/10.1145/348019.348570},
doi = {10.1145/348019.348570},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/PandaDN00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PandaNDN99,
author = {Preeti Ranjan Panda and
Hiroshi Nakamura and
Nikil D. Dutt and
Alexandru Nicolau},
title = {Augmenting Loop Tiling with Data Alignment for Improved Cache Performance},
journal = {{IEEE} Trans. Computers},
volume = {48},
number = {2},
pages = {142--149},
year = {1999},
url = {https://doi.org/10.1109/12.752655},
doi = {10.1109/12.752655},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/PandaNDN99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PandaDN99,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau},
title = {Local memory exploration and optimization in embedded systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {1},
pages = {3--13},
year = {1999},
url = {https://doi.org/10.1109/43.739054},
doi = {10.1109/43.739054},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PandaDN99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PandaD99,
author = {Preeti Ranjan Panda and
Nikil D. Dutt},
title = {Low-power memory mapping through reducing address bus activity},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {7},
number = {3},
pages = {309--320},
year = {1999},
url = {https://doi.org/10.1109/92.784092},
doi = {10.1109/92.784092},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PandaD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/Panda99,
author = {Preeti Ranjan Panda},
editor = {Jacob K. White and
Ellen Sentovich},
title = {Memory bank customization and assignment in behavioral synthesis},
booktitle = {Proceedings of the 1999 {IEEE/ACM} International Conference on Computer-Aided
Design, 1999, San Jose, California, USA, November 7-11, 1999},
pages = {477--481},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCAD.1999.810697},
doi = {10.1109/ICCAD.1999.810697},
timestamp = {Mon, 08 May 2023 21:43:38 +0200},
biburl = {https://dblp.org/rec/conf/iccad/Panda99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PandaDN98,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau},
title = {Incorporating {DRAM} access modes into high-level synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {96--109},
year = {1998},
url = {https://doi.org/10.1109/43.681260},
doi = {10.1109/43.681260},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PandaDN98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PandaDN98,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau},
editor = {Patrick M. Dewilde and
Franz J. Rammig and
Gerry Musgrave},
title = {Data Cache Sizing for Embedded Processor Applications},
booktitle = {1998 Design, Automation and Test in Europe {(DATE} '98), February
23-26, 1998, Le Palais des Congr{\`{e}}s de Paris, Paris, France},
pages = {925--926},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/DATE.1998.655972},
doi = {10.1109/DATE.1998.655972},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PandaDN98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PandaDN97,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau},
title = {Memory data organization for improved cache performance in embedded
processor applications},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {2},
number = {4},
pages = {384--409},
year = {1997},
url = {https://doi.org/10.1145/268424.268464},
doi = {10.1145/268424.268464},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/PandaDN97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PandaDN97,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau},
title = {Efficient utilization of scratch-pad memory in embedded processor
applications},
booktitle = {European Design and Test Conference, ED{\&}TC '97, Paris, France,
17-20 March 1997},
pages = {7--11},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/EDTC.1997.582323},
doi = {10.1109/EDTC.1997.582323},
timestamp = {Fri, 20 May 2022 15:59:03 +0200},
biburl = {https://dblp.org/rec/conf/date/PandaDN97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PandaDN97,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau},
editor = {Ralph H. J. M. Otten and
Hiroto Yasuura},
title = {Exploiting off-chip memory access modes in high-level synthesis},
booktitle = {Proceedings of the 1997 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1997, San Jose, CA, USA, November 9-13, 1997},
pages = {333--340},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1997},
url = {https://doi.org/10.1109/ICCAD.1997.643539},
doi = {10.1109/ICCAD.1997.643539},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PandaDN97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PandaNDN97,
author = {Preeti Ranjan Panda and
Hiroshi Nakamura and
Nikil D. Dutt and
Alexandru Nicolau},
title = {A Data Alignment Technique for Improving Cache Performance},
booktitle = {Proceedings 1997 International Conference on Computer Design: {VLSI}
in Computers {\&} Processors, {ICCD} '97, Austin, Texas, USA,
October 12-15, 1997},
pages = {587--592},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICCD.1997.628925},
doi = {10.1109/ICCD.1997.628925},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PandaNDN97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/irregular/PandaNDN97,
author = {Preeti Ranjan Panda and
Hiroshi Nakamura and
Nikil D. Dutt and
Alexandru Nicolau},
editor = {Gianfranco Bilardi and
Afonso Ferreira and
Reinhard L{\"{u}}ling and
Jos{\'{e}} D. P. Rolim},
title = {Improving cache Performance Through Tiling and Data Alignment},
booktitle = {Solving Irregularly Structured Problems in Parallel, 4th International
Symposium, {IRREGULAR} '97, Paderborn, Germany, June 12-13, 1997,
Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1253},
pages = {167--185},
publisher = {Springer},
year = {1997},
url = {https://doi.org/10.1007/3-540-63138-0\_16},
doi = {10.1007/3-540-63138-0\_16},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/irregular/PandaNDN97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isss/PandaDN97,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau},
editor = {Frank Vahid and
Francky Catthoor},
title = {Architectural Exploration and Optimization of Local Memory in Embedded
Systems},
booktitle = {Proceedings of the 10th International Symposium on System Synthesis,
{ISSS} '97, Antwerp, Belgium, September 17-19, 1997},
pages = {90},
publisher = {{ACM} / {IEEE} Computer Society},
year = {1997},
url = {https://doi.ieeecomputersociety.org/10.1109/ISSS.1997.621680},
doi = {10.1109/ISSS.1997.621680},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isss/PandaDN97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PandaD97,
author = {Preeti Ranjan Panda and
Nikil D. Dutt},
title = {Behavioral Array Mapping into Multiport Memories Targeting Low Power},
booktitle = {10th International Conference on {VLSI} Design {(VLSI} Design 1997),
4-7 January 1997, Hyderabad, India},
pages = {268--273},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICVD.1997.568088},
doi = {10.1109/ICVD.1997.568088},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PandaD97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PandaD96,
author = {Preeti Ranjan Panda and
Nikil D. Dutt},
title = {Reducing Address Bus Transitions for Low Power Memory Mapping},
booktitle = {1996 European Design and Test Conference, ED{\&}TC 1996, Paris,
France, March 11-14, 1996},
pages = {63--71},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/EDTC.1996.494129},
doi = {10.1109/EDTC.1996.494129},
timestamp = {Fri, 20 May 2022 15:52:30 +0200},
biburl = {https://dblp.org/rec/conf/date/PandaD96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/PandaD96,
author = {Preeti Ranjan Panda and
Nikil D. Dutt},
editor = {Mark Horowitz and
Jan M. Rabaey and
Brock Barton and
Massoud Pedram},
title = {Low-power mapping of behavioral arrays to multiple memories},
booktitle = {Proceedings of the 1996 International Symposium on Low Power Electronics
and Design, 1996, Monterey, California, USA, August 12-14, 1996},
pages = {289--292},
publisher = {{IEEE}},
year = {1996},
url = {https://doi.org/10.1109/LPE.1996.547525},
doi = {10.1109/LPE.1996.547525},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/islped/PandaD96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isss/PandaDN96,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau},
title = {Memory Organization for Improved Data Cache Performance in Embedded
Processors},
booktitle = {Proceedings of the 9th International Symposium on System Synthesis,
{ISSS} '96, San Diego, CA, USA, November 6-8, 1996},
pages = {90--95},
publisher = {{ACM} / {IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ISSS.1996.565886},
doi = {10.1109/ISSS.1996.565886},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isss/PandaDN96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isss/PandaD95,
author = {Preeti Ranjan Panda and
Nikil D. Dutt},
editor = {Pierre G. Paulin and
Farhad Mavaddat},
title = {1995 high level synthesis design repository},
booktitle = {Proceedings of the 8th International Symposium on System Synthesis
{(ISSS} 1995), September 13-15, 1995, Cannes, France},
pages = {170--174},
publisher = {{ACM}},
year = {1995},
url = {https://doi.org/10.1145/224486.224537},
doi = {10.1145/224486.224537},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isss/PandaD95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/MitraPC93,
author = {Biswadip Mitra and
Preeti Ranjan Panda and
Parimal Pal Chaudhuri},
title = {Estimating the Complexity of Synthesized Designs from {FSM} Specifications},
journal = {{IEEE} Des. Test Comput.},
volume = {10},
number = {1},
pages = {30--35},
year = {1993},
url = {https://doi.org/10.1109/54.199802},
doi = {10.1109/54.199802},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/MitraPC93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/MitraPC92,
author = {Biswadip Mitra and
Preeti Ranjan Panda and
Parimal Pal Chaudhuri},
title = {Estimating the Complexity of Synthesized Designs from {FSM} Specifications},
booktitle = {Proceedings of the Fifth International Conference on {VLSI} Design,
{VLSI} Design 1992, Bangalore, India, January 4-7, 1992},
pages = {175--180},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/ICVD.1992.658043},
doi = {10.1109/ICVD.1992.658043},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/MitraPC92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MitraPC91,
author = {Biswadip Mitra and
Preeti Ranjan Panda and
Parimal Pal Chaudhuri},
title = {A Flexible Scheme for State Assignment Based on Characteristics of
the {FSM}},
booktitle = {1991 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of
Technical Papers},
pages = {226--229},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/ICCAD.1991.185238},
doi = {10.1109/ICCAD.1991.185238},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MitraPC91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-03-24 00:12 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
