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ORCIDBibTeX records: Hadi Parandeh-Afshar
@inproceedings{DBLP:conf/aspdac/BoroumandPBM18,
author = {Sina Boroumand and
Hadi Parandeh{-}Afshar and
Philip Brisk and
Siamak Mohammadi},
editor = {Youngsoo Shin},
title = {Exploration of approximate multipliers design space using carry propagation
free compressors},
booktitle = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2018, Jeju, Korea (South), January 22-25, 2018},
pages = {611--616},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASPDAC.2018.8297390},
doi = {10.1109/ASPDAC.2018.8297390},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/BoroumandPBM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BoroumandPB18,
author = {Sina Boroumand and
Hadi Parandeh{-}Afshar and
Philip Brisk},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Approximate quaternary addition with the fast carry chains of FPGAs},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {577--580},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342073},
doi = {10.23919/DATE.2018.8342073},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/BoroumandPB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/BoroumandPBM17,
author = {Sina Boroumand and
Hadi Parandeh{-}Afshar and
Philip Brisk and
Siamak Mohammadi},
title = {{CAL:} Exploring cost, accuracy, and latency in approximate and speculative
adder design},
booktitle = {{IEEE} International Symposium on Defect and Fault Tolerance in {VLSI}
and Nanotechnology Systems, {DFT} 2017, Cambridge, United Kingdom,
October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/DFT.2017.8244438},
doi = {10.1109/DFT.2017.8244438},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/BoroumandPBM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ZgheibYHNPYI14,
author = {Grace Zgheib and
Liqun Yang and
Zhihong Huang and
David Novo and
Hadi Parandeh{-}Afshar and
Haigang Yang and
Paolo Ienne},
editor = {Vaughn Betz and
George A. Constantinides},
title = {Revisiting and-inverter cones},
booktitle = {The 2014 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} '14, Monterey, CA, {USA} - February 26 - 28, 2014},
pages = {45--54},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2554688.2554791},
doi = {10.1145/2554688.2554791},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ZgheibYHNPYI14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Parandeh-AfsharZNPI13,
author = {Hadi Parandeh{-}Afshar and
Grace Zgheib and
David Novo and
Madhura Purnaprajna and
Paolo Ienne},
editor = {Brad L. Hutchings and
Vaughn Betz},
title = {Shadow AICs: reaping the benefits of and-inverter cones with minimal
architectural impact (abstract only)},
booktitle = {The 2013 {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} '13, Monterey, CA, USA, February 11-13, 2013},
pages = {279},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2435264.2435348},
doi = {10.1145/2435264.2435348},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Parandeh-AfsharZNPI13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/Parandeh-AfsharZNPI13,
author = {Hadi Parandeh{-}Afshar and
Grace Zgheib and
David Novo and
Madhura Purnaprajna and
Paolo Ienne},
title = {Shadow And-Inverter Cones},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645566},
doi = {10.1109/FPL.2013.6645566},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/Parandeh-AfsharZNPI13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/ch/Afshar12,
author = {Hadi Parandeh{-}Afshar},
title = {Closing the Gap between {FPGA} and {ASIC} - Balancing Flexibility
and Efficiency},
school = {EPFL, Switzerland},
year = {2012},
url = {https://doi.org/10.5075/epfl-thesis-5339},
doi = {10.5075/EPFL-THESIS-5339},
timestamp = {Fri, 29 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/ch/Afshar12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Parandeh-AfsharBNI12,
author = {Hadi Parandeh{-}Afshar and
Hind Benbihi and
David Novo and
Paolo Ienne},
editor = {Katherine Compton and
Brad L. Hutchings},
title = {Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter
cones},
booktitle = {Proceedings of the {ACM/SIGDA} 20th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2012, Monterey, California, USA,
February 22-24, 2012},
pages = {119--128},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2145694.2145715},
doi = {10.1145/2145694.2145715},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Parandeh-AfsharBNI12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MoctarGPILB12,
author = {Yehdhih Ould Mohammed Moctar and
Nithin George and
Hadi Parandeh{-}Afshar and
Paolo Ienne and
Guy G. F. Lemieux and
Philip Brisk},
editor = {Katherine Compton and
Brad L. Hutchings},
title = {Reducing the cost of floating-point mantissa alignment and normalization
in FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 20th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2012, Monterey, California, USA,
February 22-24, 2012},
pages = {255--264},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2145694.2145738},
doi = {10.1145/2145694.2145738},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MoctarGPILB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Parandeh-AfsharNBI11,
author = {Hadi Parandeh{-}Afshar and
Arkosnato Neogy and
Philip Brisk and
Paolo Ienne},
title = {Compressor tree synthesis on commercial high-performance FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {39:1--39:19},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068725},
doi = {10.1145/2068716.2068725},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Parandeh-AfsharNBI11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Parandeh-AfsharZBI11,
author = {Hadi Parandeh{-}Afshar and
Grace Zgheib and
Philip Brisk and
Paolo Ienne},
editor = {John Wawrzynek and
Katherine Compton},
title = {Reducing the pressure on routing resources of FPGAs with generic logic
chains},
booktitle = {Proceedings of the {ACM/SIGDA} 19th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2011, Monterey, California, USA,
February 27, March 1, 2011},
pages = {237--246},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1950413.1950458},
doi = {10.1145/1950413.1950458},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Parandeh-AfsharZBI11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/Parandeh-AfsharI11,
author = {Hadi Parandeh{-}Afshar and
Paolo Ienne},
title = {Measuring and Reducing the Performance Gap between Embedded and Soft
Multipliers on FPGAs},
booktitle = {International Conference on Field Programmable Logic and Applications,
{FPL} 2011, September 5-7, Chania, Crete, Greece},
pages = {225--231},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/FPL.2011.48},
doi = {10.1109/FPL.2011.48},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/Parandeh-AfsharI11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Parandeh-AfsharVBI10,
author = {Hadi Parandeh{-}Afshar and
Ajay Kumar Verma and
Philip Brisk and
Paolo Ienne},
title = {Improving {FPGA} Performance for Carry-Save Arithmetic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {4},
pages = {578--590},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2009.2014380},
doi = {10.1109/TVLSI.2009.2014380},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Parandeh-AfsharVBI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/Parandeh-AfsharI10,
author = {Hadi Parandeh{-}Afshar and
Paolo Ienne},
editor = {Ron Sass and
Russell Tessier},
title = {Highly Versatile {DSP} Blocks for Improved {FPGA} Arithmetic Performance},
booktitle = {18th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2010, Charlotte, North Carolina, USA, 2-4
May 2010},
pages = {229--236},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/FCCM.2010.42},
doi = {10.1109/FCCM.2010.42},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/Parandeh-AfsharI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/VermaVPBI10,
author = {Amit Verma and
Ajay Kumar Verma and
Hadi Parandeh{-}Afshar and
Philip Brisk and
Paolo Ienne},
title = {Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save
Arithmetic},
booktitle = {International Conference on Field Programmable Logic and Applications,
{FPL} 2010, August 31 2010 - September 2, 2010, Milano, Italy},
pages = {19--24},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/FPL.2010.15},
doi = {10.1109/FPL.2010.15},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/VermaVPBI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CevreroAPVNNGBLI09,
author = {Alessandro Cevrero and
Panagiotis Athanasopoulos and
Hadi Parandeh{-}Afshar and
Ajay Kumar Verma and
Seyed{-}Hosein Attarzadeh{-}Niaki and
Chrysostomos Nicopoulos and
Frank K. G{\"{u}}rkaynak and
Philip Brisk and
Yusuf Leblebici and
Paolo Ienne},
title = {Field Programmable Compressor Trees: Acceleration of Multi-Input Addition
on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {13:1--13:36},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534923},
doi = {10.1145/1534916.1534923},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/CevreroAPVNNGBLI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Parandeh-AfsharBI09,
author = {Hadi Parandeh{-}Afshar and
Philip Brisk and
Paolo Ienne},
title = {An {FPGA} Logic Cell and Carry Chain Configurable as a 6: 2 or 7:
2 Compressor},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {3},
pages = {19:1--19:42},
year = {2009},
url = {https://doi.org/10.1145/1575774.1575778},
doi = {10.1145/1575774.1575778},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Parandeh-AfsharBI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CevreroAPBLIS09,
author = {Alessandro Cevrero and
Panagiotis Athanasopoulos and
Hadi Parandeh{-}Afshar and
Philip Brisk and
Yusuf Leblebici and
Paolo Ienne and
Maurizio Skerlj},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {3D configuration caching for 2D FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {286},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508205},
doi = {10.1145/1508128.1508205},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/CevreroAPBLIS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/Parandeh-AfsharBI09,
author = {Hadi Parandeh{-}Afshar and
Philip Brisk and
Paolo Ienne},
editor = {Martin Danek and
Jiri Kadlec and
Brent E. Nelson},
title = {Exploiting fast carry-chains of FPGAs for designing compressor trees},
booktitle = {19th International Conference on Field Programmable Logic and Applications,
{FPL} 2009, August 31 - September 2, 2009, Prague, Czech Republic},
pages = {242--249},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/FPL.2009.5272301},
doi = {10.1109/FPL.2009.5272301},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/Parandeh-AfsharBI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/CevreroAPSBLI09,
author = {Alessandro Cevrero and
Panagiotis Athanasopoulos and
Hadi Parandeh{-}Afshar and
Maurizio Skerlj and
Philip Brisk and
Yusuf Leblebici and
Paolo Ienne},
editor = {Martin Danek and
Jiri Kadlec and
Brent E. Nelson},
title = {Using 3D integration technology to realize multi-context FPGAs},
booktitle = {19th International Conference on Field Programmable Logic and Applications,
{FPL} 2009, August 31 - September 2, 2009, Prague, Czech Republic},
pages = {507--510},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/FPL.2009.5272454},
doi = {10.1109/FPL.2009.5272454},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/CevreroAPSBLI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/Parandeh-AfsharCABLI09,
author = {Hadi Parandeh{-}Afshar and
Alessandro Cevrero and
Panagiotis Athanasopoulos and
Philip Brisk and
Yusuf Leblebici and
Paolo Ienne},
editor = {Neil W. Bergmann and
Oliver Diessel and
Lesley Shannon},
title = {A flexible {DSP} block to enhance {FPGA} arithmetic performance},
booktitle = {Proceedings of the 2009 International Conference on Field-Programmable
Technology, {FPT} 2009, Sydney, Australia, December 9-11, 2009},
pages = {70--77},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/FPT.2009.5377638},
doi = {10.1109/FPT.2009.5377638},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/Parandeh-AfsharCABLI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Parandeh-AfsharBI08,
author = {Hadi Parandeh{-}Afshar and
Philip Brisk and
Paolo Ienne},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Efficient synthesis of compressor trees on FPGAs},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {138--143},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4483927},
doi = {10.1109/ASPDAC.2008.4483927},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/Parandeh-AfsharBI08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/Parandeh-AfsharBI08,
author = {Hadi Parandeh{-}Afshar and
Philip Brisk and
Paolo Ienne},
editor = {Donatella Sciuto},
title = {Improving Synthesis of Compressor Trees on FPGAs via Integer Linear
Programming},
booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany,
March 10-14, 2008},
pages = {1256--1261},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1109/DATE.2008.4484851},
doi = {10.1109/DATE.2008.4484851},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/Parandeh-AfsharBI08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Parandeh-AfsharBI08,
author = {Hadi Parandeh{-}Afshar and
Philip Brisk and
Paolo Ienne},
editor = {Mike Hutton and
Paul Chow},
title = {A novel {FPGA} logic block for improved arithmetic performance},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {171--180},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344698},
doi = {10.1145/1344671.1344698},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Parandeh-AfsharBI08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CevreroAPVBGLI08,
author = {Alessandro Cevrero and
Panagiotis Athanasopoulos and
Hadi Parandeh{-}Afshar and
Ajay Kumar Verma and
Philip Brisk and
Frank K. G{\"{u}}rkaynak and
Yusuf Leblebici and
Paolo Ienne},
editor = {Mike Hutton and
Paul Chow},
title = {Architectural improvements for field programmable counter arrays:
enabling efficient synthesis of fast compressor trees on FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {181--190},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344699},
doi = {10.1145/1344671.1344699},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/CevreroAPVBGLI08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Parandeh-AfsharSAP07,
author = {Hadi Parandeh{-}Afshar and
Mohsen Saneei and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {Fast {INC-XOR} codec for low-power address buses},
journal = {{IET} Comput. Digit. Tech.},
volume = {1},
number = {5},
pages = {625--626},
year = {2007},
url = {https://doi.org/10.1049/iet-cdt:20070056},
doi = {10.1049/IET-CDT:20070056},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Parandeh-AfsharSAP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/BriskVIP07,
author = {Philip Brisk and
Ajay Kumar Verma and
Paolo Ienne and
Hadi Parandeh{-}Afshar},
title = {Enhancing {FPGA} Performance for Arithmetic Circuits},
booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007,
San Diego, CA, USA, June 4-8, 2007},
pages = {334--337},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1145/1278480.1278565},
doi = {10.1145/1278480.1278565},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/BriskVIP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/Parandeh-AfsharAS06,
author = {Hadi Parandeh{-}Afshar and
Mohsen Ahmadvand and
Saeed Safari},
title = {A Novel Merged Multiplier-Accumulator Embedded in {DSP} Coprocessor},
booktitle = {13th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2006, Nice, France, December 10-13, 2006},
pages = {119--122},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ICECS.2006.379734},
doi = {10.1109/ICECS.2006.379734},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/Parandeh-AfsharAS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/Parandeh-AfsharAK06,
author = {Hadi Parandeh{-}Afshar and
Ali Afzali{-}Kusha and
Ali Khaki{-}Firooz},
title = {A very high performance address {BUS} encoder},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692939},
doi = {10.1109/ISCAS.2006.1692939},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/Parandeh-AfsharAK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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