BibTeX records: Jaejin Park

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@article{DBLP:journals/tcas/JeongKPKPJ17,
  author       = {Gyu{-}Seob Jeong and
                  Wooseok Kim and
                  Jaejin Park and
                  Taeik Kim and
                  Hojin Park and
                  Deog{-}Kyoon Jeong},
  title        = {A 0.015-mm\({}^{\mbox{2}}\) Inductorless 32-GHz Clock Generator With
                  Wide Frequency-Tuning Range in 28-nm {CMOS} Technology},
  journal      = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
  volume       = {64-II},
  number       = {6},
  pages        = {655--659},
  year         = {2017},
  url          = {https://doi.org/10.1109/TCSII.2015.2504274},
  doi          = {10.1109/TCSII.2015.2504274},
  timestamp    = {Wed, 27 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/JeongKPKPJ17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/IvanovP16,
  author       = {Vadim Ivanov and
                  Jaejin Park},
  title        = {Session 12 overview: Efficient Power Conversion},
  booktitle    = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  pages        = {216--217},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISSCC.2016.7417984},
  doi          = {10.1109/ISSCC.2016.7417984},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/IvanovP16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/KimPPJ14,
  author       = {Wooseok Kim and
                  Jaejin Park and
                  Hojin Park and
                  Deog{-}Kyoon Jeong},
  title        = {Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital
                  Pixel Clock Generator},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {49},
  number       = {3},
  pages        = {657--672},
  year         = {2014},
  url          = {https://doi.org/10.1109/JSSC.2014.2298455},
  doi          = {10.1109/JSSC.2014.2298455},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KimPPJ14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/LiuJLSLKPP14,
  author       = {Jenlung Liu and
                  Tae{-}Kwang Jang and
                  Yonghee Lee and
                  Jungeun Shin and
                  Seunghoon Lee and
                  Taeik Kim and
                  Jaejin Park and
                  Hojin Park},
  title        = {15.2 {A} 0.012mm\({}^{\mbox{2}}\) 3.1mW bang-bang digital fractional-N
                  {PLL} with a power-supply-noise cancellation technique and a walking-one-phase-selection
                  fractional frequency divider},
  booktitle    = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
                  {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
                  February 9-13, 2014},
  pages        = {268--269},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISSCC.2014.6757429},
  doi          = {10.1109/ISSCC.2014.6757429},
  timestamp    = {Mon, 09 Aug 2021 14:54:04 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LiuJLSLKPP14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iccad/KimSYPPK13,
  author       = {Taehwan Kim and
                  Do{-}Gyoon Song and
                  Sangho Youn and
                  Jaejin Park and
                  Hojin Park and
                  Jaeha Kim},
  editor       = {J{\"{o}}rg Henkel},
  title        = {Verifying start-up failures in coupled ring oscillators in presence
                  of variability using predictive global optimization},
  booktitle    = {The {IEEE/ACM} International Conference on Computer-Aided Design,
                  ICCAD'13, San Jose, CA, USA, November 18-21, 2013},
  pages        = {486--493},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ICCAD.2013.6691161},
  doi          = {10.1109/ICCAD.2013.6691161},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iccad/KimSYPPK13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/KimPKKPJ13,
  author       = {Wooseok Kim and
                  Jaejin Park and
                  Jihyun F. Kim and
                  Taeik Kim and
                  Hojin Park and
                  Deog{-}Kyoon Jeong},
  title        = {A 0.032mm\({}^{\mbox{2}}\) 3.1mW synthesized pixel clock generator
                  with 30psrms integrated jitter and 10-to-630MHz {DCO} tuning range},
  booktitle    = {2013 {IEEE} International Solid-State Circuits Conference - Digest
                  of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
                  17-21, 2013},
  pages        = {250--251},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ISSCC.2013.6487721},
  doi          = {10.1109/ISSCC.2013.6487721},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/KimPKKPJ13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/JangXLSRKKPP13,
  author       = {Tae{-}Kwang Jang and
                  Nan Xing and
                  Frank Liu and
                  Jungeun Shin and
                  Hyungreal Ryu and
                  Jihyun F. Kim and
                  Taeik Kim and
                  Jaejin Park and
                  Hojin Park},
  title        = {A 0.026mm\({}^{\mbox{2}}\) 5.3mW 32-to-2000MHz digital fractional-N
                  phase locked-loop using a phase-interpolating phase-to-digital converter},
  booktitle    = {2013 {IEEE} International Solid-State Circuits Conference - Digest
                  of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
                  17-21, 2013},
  pages        = {254--255},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ISSCC.2013.6487723},
  doi          = {10.1109/ISSCC.2013.6487723},
  timestamp    = {Wed, 28 Jun 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/JangXLSRKKPP13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/HongKLXJPKKP12,
  author       = {Jong{-}Phil Hong and
                  Sung{-}Jin Kim and
                  Jenlung Liu and
                  Nan Xing and
                  Tae{-}Kwang Jang and
                  Jaejin Park and
                  Jihyun F. Kim and
                  Taeik Kim and
                  Hojin Park},
  title        = {A 0.004mm\({}^{\mbox{2}}\) 250{\(\mu\)}W {\(\Delta\)}{\(\Sigma\)}
                  {TDC} with time-difference accumulator and a 0.012mm\({}^{\mbox{2}}\)
                  2.5mW bang-bang digital {PLL} using {PRNG} for low-power SoC applications},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {240--242},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6176992},
  doi          = {10.1109/ISSCC.2012.6176992},
  timestamp    = {Tue, 29 Dec 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/HongKLXJPKKP12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ParkPPC12,
  author       = {Pyoungwon Park and
                  Jaejin Park and
                  Hojin Park and
                  SeongHwan Cho},
  title        = {An all-digital clock generator using a fractionally injection-locked
                  oscillator in 65nm {CMOS}},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {336--337},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6177036},
  doi          = {10.1109/ISSCC.2012.6177036},
  timestamp    = {Wed, 17 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ParkPPC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asscc/LiuJJKKPP11,
  author       = {Jenlung Liu and
                  Sehyung Jeon and
                  Tae{-}Kwang Jang and
                  Dohyung Kim and
                  Jihyun F. Kim and
                  Jaejin Park and
                  Hojin Park},
  title        = {A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator
                  in 32nm {CMOS}},
  booktitle    = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
                  South Korea, November 14-16, 2011},
  pages        = {337--340},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/ASSCC.2011.6123582},
  doi          = {10.1109/ASSCC.2011.6123582},
  timestamp    = {Tue, 29 Dec 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/asscc/LiuJJKKPP11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/bioinformatics/ParkPJKKCAKLKPJKKL08,
  author       = {Jongsun Park and
                  Jaejin Park and
                  Suwang Jang and
                  Seryun Kim and
                  Sunghyung Kong and
                  Jaeyoung Choi and
                  Kyohun Ahn and
                  Juhyeon Kim and
                  Seungmin Lee and
                  Sunggon Kim and
                  Bongsoo Park and
                  Kyongyong Jung and
                  Soonok Kim and
                  Seogchan Kang and
                  Yong{-}Hwan Lee},
  title        = {{FTFD:} an informatics pipeline supporting phylogenomic analysis of
                  fungal transcription factors},
  journal      = {Bioinform.},
  volume       = {24},
  number       = {7},
  pages        = {1024--1025},
  year         = {2008},
  url          = {https://doi.org/10.1093/bioinformatics/btn058},
  doi          = {10.1093/BIOINFORMATICS/BTN058},
  timestamp    = {Mon, 02 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/bioinformatics/ParkPJKKCAKLKPJKKL08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/nar/ParkPJJYCKPKKKKBLKL08,
  author       = {Jongsun Park and
                  Bongsoo Park and
                  Kyongyong Jung and
                  Suwang Jang and
                  Kwangyul Yu and
                  Jaeyoung Choi and
                  Sunghyung Kong and
                  Jaejin Park and
                  Seryun Kim and
                  Hyojeong Kim and
                  Soonok Kim and
                  Jihyun F. Kim and
                  Jaime E. Blair and
                  Kwangwon Lee and
                  Seogchan Kang and
                  Yong{-}Hwan Lee},
  title        = {{CFGP:} a web-based, comparative fungal genomics platform},
  journal      = {Nucleic Acids Res.},
  volume       = {36},
  number       = {Database-Issue},
  pages        = {562--571},
  year         = {2008},
  url          = {https://doi.org/10.1093/nar/gkm758},
  doi          = {10.1093/NAR/GKM758},
  timestamp    = {Sun, 17 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/nar/ParkPJJYCKPKKKKBLKL08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/cicc/ParkLCY07,
  author       = {Jaejin Park and
                  J. F. Liu and
                  L. Richard Carley and
                  C. Patrick Yue},
  title        = {A 1-V, 1.4-2.5 GHz Charge-Pump-Less {PLL} for a Phase Interpolator
                  Based {CDR}},
  booktitle    = {Proceedings of the {IEEE} 2007 Custom Integrated Circuits Conference,
                  {CICC} 2007, DoubleTree Hotel, San Jose, California, USA, September
                  16-19, 2007},
  pages        = {281--284},
  publisher    = {{IEEE}},
  year         = {2007},
  url          = {https://doi.org/10.1109/CICC.2007.4405733},
  doi          = {10.1109/CICC.2007.4405733},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/ParkLCY07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/SunPOY05,
  author       = {Ruifeng Sun and
                  Jaejin Park and
                  Frank O'Mahony and
                  C. Patrick Yue},
  title        = {A low-power, 20-Gb/s continuous-time adaptive passive equalizer},
  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
                  May 2005, Kobe, Japan},
  pages        = {920--923},
  publisher    = {{IEEE}},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCAS.2005.1464739},
  doi          = {10.1109/ISCAS.2005.1464739},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/SunPOY05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/ParkSCY05,
  author       = {Jaejin Park and
                  Ruifeng Sun and
                  L. Rick Carley and
                  C. Patrick Yue},
  title        = {A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for
                  future hard disk drive channel ICs},
  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
                  May 2005, Kobe, Japan},
  pages        = {1162--1165},
  publisher    = {{IEEE}},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCAS.2005.1464800},
  doi          = {10.1109/ISCAS.2005.1464800},
  timestamp    = {Sun, 04 Jun 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/ParkSCY05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/ParkPKSC00,
  author       = {Jaejin Park and
                  Ho{-}Jin Park and
                  Jae{-}Whui Kim and
                  Sangnam Seo and
                  Philip Chung},
  title        = {A 1 mW 10-bit 500KSPS {SAR} {A/D} converter},
  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
                  Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
                  May 2000, Proceedings},
  pages        = {581--584},
  publisher    = {{IEEE}},
  year         = {2000},
  url          = {https://doi.org/10.1109/ISCAS.2000.857501},
  doi          = {10.1109/ISCAS.2000.857501},
  timestamp    = {Fri, 13 Aug 2021 09:26:01 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/ParkPKSC00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ParkJCS99,
  author       = {Jaejin Park and
                  Eurho Joe and
                  Myung{-}Jun Choe and
                  Bang{-}Sup Song},
  title        = {A 5-MHz {IF} digital {FM} demodulator},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {34},
  number       = {1},
  pages        = {3--11},
  year         = {1999},
  url          = {https://doi.org/10.1109/4.736650},
  doi          = {10.1109/4.736650},
  timestamp    = {Tue, 05 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ParkJCS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/KimPKJK95,
  author       = {Daejeong Kim and
                  Jaejin Park and
                  Sungjoon Kim and
                  Deog{-}Kyoon Jeong and
                  Wonchan Kim},
  title        = {A single chip i{\(\Delta\)}-{\(\Sigma\)} {ADC} with a built-in variable
                  gain stage and {DAC} with a charge integrating subconverter for a
                  5 {V} 9600-b/s modem},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {30},
  number       = {8},
  pages        = {940--943},
  year         = {1995},
  url          = {https://doi.org/10.1109/4.408364},
  doi          = {10.1109/4.408364},
  timestamp    = {Tue, 09 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KimPKJK95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/KimPKJK94,
  author       = {Daejong Kim and
                  Jaejin Park and
                  Sungjoon Kim and
                  Deog{-}Kyoon Jeong and
                  Wonchan Kim},
  title        = {A Multibit Delta-Sigma {D/A} Converter Using a Charge Integrating
                  Sub-Converter},
  booktitle    = {1994 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
                  1994, London, England, UK, May 30 - June 2, 1994},
  pages        = {319--322},
  publisher    = {{IEEE}},
  year         = {1994},
  url          = {https://doi.org/10.1109/ISCAS.1994.409261},
  doi          = {10.1109/ISCAS.1994.409261},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/KimPKJK94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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