BibTeX records: Jihong Ren

download as .bib file

@article{DBLP:journals/lgrs/JiCWSZJRL23,
  author       = {Yonggang Ji and
                  Xiaoyu Cheng and
                  Yiming Wang and
                  Weifeng Sun and
                  Xi Zhang and
                  Meicheng Jiang and
                  Jihong Ren and
                  Farui Li},
  title        = {Motion Compensation Method Using Direct Wave Signal for {CTSR} Bistatic
                  {HFSWR}},
  journal      = {{IEEE} Geosci. Remote. Sens. Lett.},
  volume       = {20},
  pages        = {1--5},
  year         = {2023},
  url          = {https://doi.org/10.1109/LGRS.2023.3249347},
  doi          = {10.1109/LGRS.2023.3249347},
  timestamp    = {Mon, 25 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/lgrs/JiCWSZJRL23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/NavidCHLRCDASLS15,
  author       = {Reza Navid and
                  E{-}Hung Chen and
                  Masum Hossain and
                  Brian S. Leibowitz and
                  Jihong Ren and
                  Chuen{-}Huei Adam Chou and
                  Barry Daly and
                  Marko Aleksic and
                  Bruce Su and
                  Simon Li and
                  Makarand Shirasgaonkar and
                  Fred Heaton and
                  Jared Zerbe and
                  John C. Eble},
  title        = {A 40 Gb/s Serial Link Transceiver in 28 nm {CMOS} Technology},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {50},
  number       = {4},
  pages        = {814--827},
  year         = {2015},
  url          = {https://doi.org/10.1109/JSSC.2014.2374176},
  doi          = {10.1109/JSSC.2014.2374176},
  timestamp    = {Fri, 08 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/NavidCHLRCDASLS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChenHLNRCDASLSH14,
  author       = {E{-}Hung Chen and
                  Masum Hossain and
                  Brian S. Leibowitz and
                  Reza Navid and
                  Jihong Ren and
                  Chuen{-}Huei Adam Chou and
                  Barry Daly and
                  Marko Aleksic and
                  Bruce Su and
                  Simon Li and
                  Makarand Shirasgaonkar and
                  Fred Heaton and
                  Jared Zerbe and
                  John C. Eble},
  title        = {A 40-Gb/s serial link transceiver in 28-nm {CMOS} technology},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2014, Digest of Technical Papers,
                  Honolulu, HI, USA, June 10-13, 2014},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/VLSIC.2014.6858361},
  doi          = {10.1109/VLSIC.2014.6858361},
  timestamp    = {Fri, 08 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/ChenHLNRCDASLSH14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HossainCNLCLPRD14,
  author       = {Masum Hossain and
                  E{-}Hung Chen and
                  Reza Navid and
                  Brian S. Leibowitz and
                  Chuen{-}Huei Adam Chou and
                  Simon Li and
                  Myeong{-}Jae Park and
                  Jihong Ren and
                  Barry Daly and
                  Bruce Su and
                  Makarand Shirasgaonkar and
                  Fred Heaton and
                  Jared Zerbe and
                  John C. Eble},
  title        = {A 4{\texttimes}40 Gb/s quad-lane {CDR} with shared frequency tracking
                  and data dependent jitter filtering},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2014, Digest of Technical Papers,
                  Honolulu, HI, USA, June 10-13, 2014},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/VLSIC.2014.6858362},
  doi          = {10.1109/VLSIC.2014.6858362},
  timestamp    = {Fri, 08 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/HossainCNLCLPRD14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KavianiHNHRZ12,
  author       = {Kambiz Kaviani and
                  Masum Hossain and
                  Meisam Honarvar Nazari and
                  Fred Heaton and
                  Jihong Ren and
                  Jared Zerbe},
  title        = {A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer
                  in 40-nm low-power {CMOS}},
  booktitle    = {Proceedings of the {IEEE} 2012 Custom Integrated Circuits Conference,
                  {CICC} 2012, San Jose, CA, USA, September 9-12, 2012},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/CICC.2012.6330684},
  doi          = {10.1109/CICC.2012.6330684},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/KavianiHNHRZ12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ZerbeDLSDESRLBSLLK11,
  author       = {Jared Zerbe and
                  Barry Daly and
                  Lei Luo and
                  Bill Stonecypher and
                  Wayne D. Dettloff and
                  John C. Eble and
                  Teva Stone and
                  Jihong Ren and
                  Brian S. Leibowitz and
                  Michael Bucher and
                  Patrick Satarzadeh and
                  Qi Lin and
                  Yue Lu and
                  Ravi T. Kollipara},
  title        = {A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking
                  Techniques},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {46},
  number       = {4},
  pages        = {974--985},
  year         = {2011},
  url          = {https://doi.org/10.1109/JSSC.2011.2108120},
  doi          = {10.1109/JSSC.2011.2108120},
  timestamp    = {Wed, 22 Nov 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/ZerbeDLSDESRLBSLLK11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KimCRLSZY11,
  author       = {Jaeha Kim and
                  E{-}Hung Chen and
                  Jihong Ren and
                  Brian S. Leibowitz and
                  Patrick Satarzadeh and
                  Jared Zerbe and
                  Chih{-}Kong Ken Yang},
  title        = {Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {58-I},
  number       = {9},
  pages        = {2096--2107},
  year         = {2011},
  url          = {https://doi.org/10.1109/TCSI.2011.2162465},
  doi          = {10.1109/TCSI.2011.2162465},
  timestamp    = {Fri, 08 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/KimCRLSZY11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KimRLSAZ10,
  author       = {Jaeha Kim and
                  Jihong Ren and
                  Brian S. Leibowitz and
                  Patrick Satarzadeh and
                  Ali{-}Azam Abbasfar and
                  Jared Zerbe},
  editor       = {Jacqueline Snyder and
                  Rakesh Patel and
                  Tom Andre},
  title        = {Equalizer design and performance trade-offs in ADC-based serial links},
  booktitle    = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2010, San Jose,
                  California, USA, 19-22 September, 2010, Proceedings},
  pages        = {1--8},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/CICC.2010.5617601},
  doi          = {10.1109/CICC.2010.5617601},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/KimRLSAZ10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KimLRM09,
  author       = {Jaeha Kim and
                  Brian S. Leibowitz and
                  Jihong Ren and
                  Chris J. Madden},
  title        = {Simulation and Analysis of Random Decision Errors in Clocked Comparators},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {56-I},
  number       = {8},
  pages        = {1844--1857},
  year         = {2009},
  url          = {https://doi.org/10.1109/TCSI.2009.2028449},
  doi          = {10.1109/TCSI.2009.2028449},
  timestamp    = {Fri, 22 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/KimLRM09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KimRH09,
  author       = {Jaeha Kim and
                  Jihong Ren and
                  Mark A. Horowitz},
  title        = {Stochastic steady-state and {AC} analyses of mixed-signal systems},
  booktitle    = {Proceedings of the 46th Design Automation Conference, {DAC} 2009,
                  San Francisco, CA, USA, July 26-31, 2009},
  pages        = {376--381},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1629911.1630011},
  doi          = {10.1145/1629911.1630011},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dac/KimRH09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChenRLLLOLSZY08,
  author       = {E{-}Hung Chen and
                  Jihong Ren and
                  Brian S. Leibowitz and
                  Hae{-}Chang Lee and
                  Qi Lin and
                  Kyung Suk Oh and
                  Frank Lambrecht and
                  Vladimir Stojanovic and
                  Jared Zerbe and
                  Chih{-}Kong Ken Yang},
  title        = {Near-Optimal Equalizer and Timing Adaptation for {I/O} Links Using
                  a BER-Based Metric},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {43},
  number       = {9},
  pages        = {2144--2156},
  year         = {2008},
  url          = {https://doi.org/10.1109/JSSC.2008.2001871},
  doi          = {10.1109/JSSC.2008.2001871},
  timestamp    = {Fri, 08 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ChenRLLLOLSZY08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/LeibowitzKRM08,
  author       = {Brian S. Leibowitz and
                  Jaeha Kim and
                  Jihong Ren and
                  Chris J. Madden},
  title        = {Characterization of random decision errors in clocked comparators},
  booktitle    = {Proceedings of the {IEEE} 2008 Custom Integrated Circuits Conference,
                  {CICC} 2008, DoubleTree Hotel, San Jose, California, USA, September
                  21-24, 2008},
  pages        = {691--694},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/CICC.2008.4672180},
  doi          = {10.1109/CICC.2008.4672180},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/LeibowitzKRM08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/nla/RenGG07,
  author       = {Jihong Ren and
                  Chen Greif and
                  Mark R. Greenstreet},
  title        = {An efficient linear programming solver for optimal filter synthesis},
  journal      = {Numer. Linear Algebra Appl.},
  volume       = {14},
  number       = {9},
  pages        = {695--712},
  year         = {2007},
  url          = {https://doi.org/10.1002/nla.547},
  doi          = {10.1002/NLA.547},
  timestamp    = {Mon, 28 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/nla/RenGG07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/YangGR07,
  author       = {Suwen Yang and
                  Mark R. Greenstreet and
                  Jihong Ren},
  title        = {A Jitter Attenuating Timing Chain},
  booktitle    = {13th {IEEE} International Symposium on Asynchronous Circuits and Systems
                  {(ASYNC} 2007), 12-14 March 2006, Berkeley, California, {USA}},
  pages        = {25--38},
  publisher    = {{IEEE} Computer Society},
  year         = {2007},
  url          = {https://doi.org/10.1109/ASYNC.2007.8},
  doi          = {10.1109/ASYNC.2007.8},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/YangGR07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/GreenstreetR06,
  author       = {Mark R. Greenstreet and
                  Jihong Ren},
  title        = {Surfing Interconnect},
  booktitle    = {12th {IEEE} International Symposium on Asynchronous Circuits and Systems
                  {(ASYNC} 2006), 13-15 March 2006, Grenoble, France},
  pages        = {98--106},
  publisher    = {{IEEE} Computer Society},
  year         = {2006},
  url          = {https://doi.org/10.1109/ASYNC.2006.28},
  doi          = {10.1109/ASYNC.2006.28},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/GreenstreetR06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/RenG05,
  author       = {Jihong Ren and
                  Mark R. Greenstreet},
  editor       = {William H. Joyner Jr. and
                  Grant Martin and
                  Andrew B. Kahng},
  title        = {A unified optimization framework for equalization filter synthesis},
  booktitle    = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
                  San Diego, CA, USA, June 13-17, 2005},
  pages        = {638--643},
  publisher    = {{ACM}},
  year         = {2005},
  url          = {https://doi.org/10.1145/1065579.1065747},
  doi          = {10.1145/1065579.1065747},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dac/RenG05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/RenG04,
  author       = {Jihong Ren and
                  Mark R. Greenstreet},
  title        = {A Signal Integrity Test Bed for {PCB} Buses},
  booktitle    = {22nd {IEEE} International Conference on Computer Design: {VLSI} in
                  Computers {\&} Processors {(ICCD} 2004), 11-13 October 2004, San
                  Jose, CA, USA, Proceedings},
  pages        = {132--137},
  publisher    = {{IEEE} Computer Society},
  year         = {2004},
  url          = {https://doi.org/10.1109/ICCD.2004.1347912},
  doi          = {10.1109/ICCD.2004.1347912},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iccd/RenG04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/RenG04,
  author       = {Jihong Ren and
                  Mark R. Greenstreet},
  editor       = {Enrico Macii and
                  Odysseas G. Koufopavlou and
                  Vassilis Paliouras},
  title        = {Crosstalk Cancellation for Realistic {PCB} Buses},
  booktitle    = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
                  and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
                  Greece, September 15-17, 2004, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {3254},
  pages        = {48--57},
  publisher    = {Springer},
  year         = {2004},
  url          = {https://doi.org/10.1007/978-3-540-30205-6\_7},
  doi          = {10.1007/978-3-540-30205-6\_7},
  timestamp    = {Tue, 14 May 2019 10:00:54 +0200},
  biburl       = {https://dblp.org/rec/conf/patmos/RenG04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/RenG03,
  author       = {Jihong Ren and
                  Mark R. Greenstreet},
  title        = {Synthesizing optimal filters for crosstalk-cancellation for high-speed
                  buses},
  booktitle    = {Proceedings of the 40th Design Automation Conference, {DAC} 2003,
                  Anaheim, CA, USA, June 2-6, 2003},
  pages        = {592--597},
  publisher    = {{ACM}},
  year         = {2003},
  url          = {https://doi.org/10.1145/775832.775982},
  doi          = {10.1145/775832.775982},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dac/RenG03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/RenG03,
  author       = {Jihong Ren and
                  Mark R. Greenstreet},
  title        = {Equalizing Filter Design for Crosstalk Cancellation},
  booktitle    = {2003 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
                  2003), New Trends and Technologies for {VLSI} Systems Design, 20-21
                  February 2003, Tampa, FL, {USA}},
  pages        = {272--274},
  publisher    = {{IEEE} Computer Society},
  year         = {2003},
  url          = {https://doi.org/10.1109/ISVLSI.2003.1183496},
  doi          = {10.1109/ISVLSI.2003.1183496},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isvlsi/RenG03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics