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BibTeX records: Renji Thomas
@inproceedings{DBLP:conf/hpca/ThomasBSZT16, author = {Renji Thomas and Kristin Barber and Naser Sedaghati and Li Zhou and Radu Teodorescu}, title = {Core tunneling: Variation-aware voltage noise mitigation in GPUs}, booktitle = {2016 {IEEE} International Symposium on High Performance Computer Architecture, {HPCA} 2016, Barcelona, Spain, March 12-16, 2016}, pages = {151--162}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/HPCA.2016.7446061}, doi = {10.1109/HPCA.2016.7446061}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hpca/ThomasBSZT16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispass/ThomasST16, author = {Renji Thomas and Naser Sedaghati and Radu Teodorescu}, title = {EmerGPU: Understanding and mitigating resonance-induced voltage noise in {GPU} architectures}, booktitle = {2016 {IEEE} International Symposium on Performance Analysis of Systems and Software, {ISPASS} 2016, Uppsala, Sweden, April 17-19, 2016}, pages = {79--89}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/ISPASS.2016.7482076}, doi = {10.1109/ISPASS.2016.7482076}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispass/ThomasST16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/SkarlatosTAQPKT16, author = {Dimitrios Skarlatos and Renji Thomas and Aditya Agrawal and Shibin Qin and Robert C. N. Pilawa{-}Podgurski and Ulya R. Karpuzcu and Radu Teodorescu and Nam Sung Kim and Josep Torrellas}, title = {Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks}, booktitle = {49th Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2016, Taipei, Taiwan, October 15-19, 2016}, pages = {54:1--54:12}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/MICRO.2016.7783757}, doi = {10.1109/MICRO.2016.7783757}, timestamp = {Tue, 31 May 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/SkarlatosTAQPKT16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/cal/MillerTT12, author = {Timothy N. Miller and Renji Thomas and Radu Teodorescu}, title = {Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units}, journal = {{IEEE} Comput. Archit. Lett.}, volume = {11}, number = {2}, pages = {45--48}, year = {2012}, url = {https://doi.org/10.1109/L-CA.2011.36}, doi = {10.1109/L-CA.2011.36}, timestamp = {Sun, 15 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/cal/MillerTT12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/MillerPTST12, author = {Timothy N. Miller and Xiang Pan and Renji Thomas and Naser Sedaghati and Radu Teodorescu}, title = {Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips}, booktitle = {18th {IEEE} International Symposium on High Performance Computer Architecture, {HPCA} 2012, New Orleans, LA, USA, 25-29 February, 2012}, pages = {27--38}, publisher = {{IEEE} Computer Society}, year = {2012}, url = {https://doi.org/10.1109/HPCA.2012.6168942}, doi = {10.1109/HPCA.2012.6168942}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hpca/MillerPTST12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/MillerTPT12, author = {Timothy N. Miller and Renji Thomas and Xiang Pan and Radu Teodorescu}, title = {VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors}, booktitle = {39th International Symposium on Computer Architecture {(ISCA} 2012), June 9-13, 2012, Portland, OR, {USA}}, pages = {249--260}, publisher = {{IEEE} Computer Society}, year = {2012}, url = {https://doi.org/10.1109/ISCA.2012.6237022}, doi = {10.1109/ISCA.2012.6237022}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isca/MillerTPT12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/IEEEpact/SedaghatiTPTS11, author = {Naser Sedaghati and Renji Thomas and Louis{-}No{\"{e}}l Pouchet and Radu Teodorescu and P. Sadayappan}, editor = {Lawrence Rauchwerger and Vivek Sarkar}, title = {StVEC: {A} Vector Instruction Extension for High Performance Stencil Computation}, booktitle = {2011 International Conference on Parallel Architectures and Compilation Techniques, {PACT} 2011, Galveston, TX, USA, October 10-14, 2011}, pages = {276--287}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/PACT.2011.59}, doi = {10.1109/PACT.2011.59}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/IEEEpact/SedaghatiTPTS11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/MillerTDAT10, author = {Timothy N. Miller and Renji Thomas and James Dinan and Bruce M. Adcock and Radu Teodorescu}, title = {Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches}, booktitle = {43rd Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2010, 4-8 December 2010, Atlanta, Georgia, {USA}}, pages = {351--362}, publisher = {{IEEE} Computer Society}, year = {2010}, url = {https://doi.org/10.1109/MICRO.2010.28}, doi = {10.1109/MICRO.2010.28}, timestamp = {Tue, 31 May 2022 14:39:58 +0200}, biburl = {https://dblp.org/rec/conf/micro/MillerTDAT10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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