BibTeX records: Gary S. Tyson

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@inproceedings{DBLP:conf/sigcse/WangWZT20,
  author       = {An{-}I Andy Wang and
                  David B. Whalley and
                  Zhenghao Zhang and
                  Gary S. Tyson},
  editor       = {Jian Zhang and
                  Mark Sherriff and
                  Sarah Heckman and
                  Pamela A. Cutter and
                  Alvaro E. Monge},
  title        = {Experience of Administering Our First {S-STEM} Program to Broaden
                  Participation in Computer Science},
  booktitle    = {Proceedings of the 51st {ACM} Technical Symposium on Computer Science
                  Education, {SIGCSE} 2020, Portland, OR, USA, March 11-14, 2020},
  pages        = {535--541},
  publisher    = {{ACM}},
  year         = {2020},
  url          = {https://doi.org/10.1145/3328778.3366890},
  doi          = {10.1145/3328778.3366890},
  timestamp    = {Tue, 23 Mar 2021 10:54:19 +0100},
  biburl       = {https://dblp.org/rec/conf/sigcse/WangWZT20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/enase/YannesT19,
  author       = {Zachary Yannes and
                  Gary S. Tyson},
  editor       = {Ernesto Damiani and
                  George Spanoudakis and
                  Leszek A. Maciaszek},
  title        = {Amniote: {A} User Space Interface to the Android Runtime},
  booktitle    = {Proceedings of the 14th International Conference on Evaluation of
                  Novel Approaches to Software Engineering, {ENASE} 2019, Heraklion,
                  Crete, Greece, May 4-5, 2019},
  pages        = {59--67},
  publisher    = {SciTePress},
  year         = {2019},
  url          = {https://doi.org/10.5220/0007715400590067},
  doi          = {10.5220/0007715400590067},
  timestamp    = {Tue, 06 Jun 2023 14:58:00 +0200},
  biburl       = {https://dblp.org/rec/conf/enase/YannesT19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/BrownYLSMTR16,
  author       = {Martin K. Brown and
                  Zachary Yannes and
                  Michael Lustig and
                  Mazdak Sanati and
                  Sally A. McKee and
                  Gary S. Tyson and
                  Steven K. Reinhardt},
  title        = {Agave: {A} benchmark suite for exploring the complexities of the Android
                  software stack},
  booktitle    = {2016 {IEEE} International Symposium on Performance Analysis of Systems
                  and Software, {ISPASS} 2016, Uppsala, Sweden, April 17-19, 2016},
  pages        = {157--158},
  publisher    = {{IEEE} Computer Society},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISPASS.2016.7482089},
  doi          = {10.1109/ISPASS.2016.7482089},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ispass/BrownYLSMTR16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/DavisBGSFRCUWT15,
  author       = {B. Davis and
                  Ryan Baird and
                  Peter Gavin and
                  Magnus Sj{\"{a}}lander and
                  Ian Finlayson and
                  F. Rasapour and
                  G. Cook and
                  Gang{-}Ryung Uh and
                  David B. Whalley and
                  Gary S. Tyson},
  editor       = {Ravi Iyer and
                  Siddharth Garg},
  title        = {Scheduling instruction effects for a statically pipelined processor},
  booktitle    = {2015 International Conference on Compilers, Architecture and Synthesis
                  for Embedded Systems, {CASES} 2015, Amsterdam, The Netherlands, October
                  4-9, 2015},
  pages        = {167--176},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/CASES.2015.7324557},
  doi          = {10.1109/CASES.2015.7324557},
  timestamp    = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/cases/DavisBGSFRCUWT15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sigcse/WangTWEZ14,
  author       = {An{-}I Andy Wang and
                  Gary S. Tyson and
                  David B. Whalley and
                  Robert van Engelen and
                  Zhenghao Zhang},
  editor       = {J. D. Dougherty and
                  Kris Nagel and
                  Adrienne Decker and
                  Kurt Eiselt},
  title        = {A journey toward obtaining our first {NSF} {S-STEM} (scholarship)
                  grant},
  booktitle    = {The 45th {ACM} Technical Symposium on Computer Science Education,
                  {SIGCSE} 2014, Atlanta, GA, USA, March 5-8, 2014},
  pages        = {427--432},
  publisher    = {{ACM}},
  year         = {2014},
  url          = {https://doi.org/10.1145/2538862.2538884},
  doi          = {10.1145/2538862.2538884},
  timestamp    = {Tue, 23 Mar 2021 10:54:19 +0100},
  biburl       = {https://dblp.org/rec/conf/sigcse/WangTWEZ14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lctrts/FinlaysonDGUWST13,
  author       = {Ian Finlayson and
                  Brandon Davis and
                  Peter Gavin and
                  Gang{-}Ryung Uh and
                  David B. Whalley and
                  Magnus Sj{\"{a}}lander and
                  Gary S. Tyson},
  editor       = {Bj{\"{o}}rn Franke and
                  Jingling Xue},
  title        = {Improving processor efficiency by statically pipelining instructions},
  booktitle    = {{SIGPLAN/SIGBED} Conference on Languages, Compilers and Tools for
                  Embedded Systems 2013, {LCTES} '13, Seattle, WA, USA, June 20-21,
                  2013},
  pages        = {33--44},
  publisher    = {{ACM}},
  year         = {2013},
  url          = {https://doi.org/10.1145/2491899.2465559},
  doi          = {10.1145/2491899.2465559},
  timestamp    = {Thu, 24 Jun 2021 16:19:30 +0200},
  biburl       = {https://dblp.org/rec/conf/lctrts/FinlaysonDGUWST13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/FinlaysonUWT12,
  author       = {Ian Finlayson and
                  Gang{-}Ryung Uh and
                  David B. Whalley and
                  Gary S. Tyson},
  title        = {An Overview of Static Pipelining},
  journal      = {{IEEE} Comput. Archit. Lett.},
  volume       = {11},
  number       = {1},
  pages        = {17--20},
  year         = {2012},
  url          = {https://doi.org/10.1109/L-CA.2011.26},
  doi          = {10.1109/L-CA.2011.26},
  timestamp    = {Sun, 15 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/cal/FinlaysonUWT12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/ChangHWTW12,
  author       = {Daniel Chang and
                  Stephen Hines and
                  Paul E. West and
                  Gary S. Tyson and
                  David B. Whalley},
  title        = {Program Differentiation},
  journal      = {J. Circuits Syst. Comput.},
  volume       = {21},
  number       = {2},
  year         = {2012},
  url          = {https://doi.org/10.1142/S0218126612400075},
  doi          = {10.1142/S0218126612400075},
  timestamp    = {Tue, 25 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jcsc/ChangHWTW12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEinteract/FinlaysonUWT11,
  author       = {Ian Finlayson and
                  Gang{-}Ryung Uh and
                  David B. Whalley and
                  Gary S. Tyson},
  title        = {Improving Low Power Processor Efficiency with Static Pipelining},
  booktitle    = {15th Workshop on Interaction between Compilers and Computer Architectures,
                  {INTERACT} 2011, San Antonio, Texas, USA, February 12, 2011},
  pages        = {17--24},
  publisher    = {{IEEE} Computer Society},
  year         = {2011},
  url          = {https://doi.org/10.1109/INTERACT.2011.7},
  doi          = {10.1109/INTERACT.2011.7},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/IEEEinteract/FinlaysonUWT11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/embc/MitchellMWT11,
  author       = {Michael Mitchell and
                  Christopher R. Meyers and
                  An{-}I Andy Wang and
                  Gary S. Tyson},
  title        = {ContextProvider: Context awareness for medical monitoring applications},
  booktitle    = {33rd Annual International Conference of the {IEEE} Engineering in
                  Medicine and Biology Society, {EMBC} 2011, Boston, MA, USA, August
                  30 - Sept. 3, 2011},
  pages        = {5244--5247},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/IEMBS.2011.6091297},
  doi          = {10.1109/IEMBS.2011.6091297},
  timestamp    = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl       = {https://dblp.org/rec/conf/embc/MitchellMWT11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bcb/LiTZ10,
  author       = {Yue Li and
                  Gary S. Tyson and
                  Jinfeng Zhang},
  editor       = {Aidong Zhang and
                  Mark Borodovsky and
                  Gultekin {\"{O}}zsoyoglu and
                  Armin R. Mikler},
  title        = {Effect of sequences on the shape of protein energy landscapes},
  booktitle    = {Proceedings of the First {ACM} International Conference on Bioinformatics
                  and Computational Biology, {BCB} 2010, Niagara Falls, NY, USA, August
                  2-4, 2010},
  pages        = {35--42},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1854776.1854787},
  doi          = {10.1145/1854776.1854787},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/bcb/LiTZ10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/KulkarniWTD09,
  author       = {Prasad A. Kulkarni and
                  David B. Whalley and
                  Gary S. Tyson and
                  Jack W. Davidson},
  title        = {Practical exhaustive optimization phase order exploration and evaluation},
  journal      = {{ACM} Trans. Archit. Code Optim.},
  volume       = {6},
  number       = {1},
  pages        = {1:1--1:36},
  year         = {2009},
  url          = {https://doi.org/10.1145/1509864.1509865},
  doi          = {10.1145/1509864.1509865},
  timestamp    = {Wed, 17 Feb 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/taco/KulkarniWTD09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/BhadauriaMST09,
  author       = {Major Bhadauria and
                  Sally A. McKee and
                  Karan Singh and
                  Gary S. Tyson},
  title        = {Data Cache Techniques to Save Power and Deliver High Performance in
                  Embedded Systems},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {2},
  pages        = {65--84},
  year         = {2009},
  url          = {https://doi.org/10.1007/978-3-642-00904-4\_5},
  doi          = {10.1007/978-3-642-00904-4\_5},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/BhadauriaMST09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cf/WestPTM09,
  author       = {Paul E. West and
                  Yuval Peress and
                  Gary S. Tyson and
                  Sally A. McKee},
  editor       = {Gearold Johnson and
                  Carsten Trinitis and
                  Georgi Gaydadjiev and
                  Alexander V. Veidenbaum},
  title        = {Core monitors: monitoring performance in multicore processors},
  booktitle    = {Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia,
                  Italy, May 18-20, 2009},
  pages        = {31--40},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1531743.1531751},
  doi          = {10.1145/1531743.1531751},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/cf/WestPTM09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lctrts/HinesPGWT09,
  author       = {Stephen Roderick Hines and
                  Yuval Peress and
                  Peter Gavin and
                  David B. Whalley and
                  Gary S. Tyson},
  editor       = {Christoph M. Kirsch and
                  Mahmut T. Kandemir},
  title        = {Guaranteeing instruction fetch behavior with a lookahead instruction
                  fetch engine {(LIFE)}},
  booktitle    = {Proceedings of the 2009 {ACM} {SIGPLAN/SIGBED} conference on Languages,
                  compilers, and tools for embedded systems, {LCTES} 2009, Dublin, Ireland,
                  June 19-20, 2009},
  pages        = {119--128},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1542452.1542469},
  doi          = {10.1145/1542452.1542469},
  timestamp    = {Fri, 25 Jun 2021 14:48:54 +0200},
  biburl       = {https://dblp.org/rec/conf/lctrts/HinesPGWT09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/colcom/FigueiredoBFLPWJKLMMRT08,
  author       = {Renato J. O. Figueiredo and
                  P. Oscar Boykin and
                  Jos{\'{e}} A. B. Fortes and
                  Tao Li and
                  Jie{-}Kwon Peir and
                  David Wolinsky and
                  Lizy K. John and
                  David R. Kaeli and
                  David J. Lilja and
                  Sally A. McKee and
                  Gokhan Memik and
                  Alain Roy and
                  Gary S. Tyson},
  editor       = {Elisa Bertino and
                  James B. D. Joshi},
  title        = {Archer: {A} Community Distributed Computing Infrastructure for Computer
                  Architecture Research and Education},
  booktitle    = {Collaborative Computing: Networking, Applications and Worksharing,
                  4th International Conference, CollaborateCom 2008, Orlando, FL, USA,
                  November 13-16, 2008, Revised Selected Papers},
  series       = {Lecture Notes of the Institute for Computer Sciences, Social Informatics
                  and Telecommunications Engineering},
  volume       = {10},
  pages        = {70--84},
  publisher    = {Springer / {ICST}},
  year         = {2008},
  url          = {https://doi.org/10.1007/978-3-642-03354-4\_7},
  doi          = {10.1007/978-3-642-03354-4\_7},
  timestamp    = {Fri, 09 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/colcom/FigueiredoBFLPWJKLMMRT08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/WhalleyT08,
  author       = {David B. Whalley and
                  Gary S. Tyson},
  title        = {Enhancing the effectiveness of utilizing an instruction register file},
  booktitle    = {22nd {IEEE} International Symposium on Parallel and Distributed Processing,
                  {IPDPS} 2008, Miami, Florida USA, April 14-18, 2008},
  pages        = {1--5},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/IPDPS.2008.4536413},
  doi          = {10.1109/IPDPS.2008.4536413},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ipps/WhalleyT08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-0807-1765,
  author       = {Renato J. O. Figueiredo and
                  P. Oscar Boykin and
                  Jos{\'{e}} A. B. Fortes and
                  Tao Li and
                  Jie{-}Kwon Peir and
                  David Wolinsky and
                  Lizy Kurian John and
                  David R. Kaeli and
                  David J. Lilja and
                  Sally A. McKee and
                  Gokhan Memik and
                  Alain Roy and
                  Gary S. Tyson},
  title        = {Archer: {A} Community Distributed Computing Infrastructure for Computer
                  Architecture Research and Education},
  journal      = {CoRR},
  volume       = {abs/0807.1765},
  year         = {2008},
  url          = {http://arxiv.org/abs/0807.1765},
  eprinttype    = {arXiv},
  eprint       = {0807.1765},
  timestamp    = {Tue, 15 Jan 2019 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/corr/abs-0807-1765.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/GeigerMT07,
  author       = {Michael J. Geiger and
                  Sally A. McKee and
                  Gary S. Tyson},
  title        = {Specializing Cache Structures for High Performance and Energy Conservation
                  in Embedded Systems},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {54--73},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_5},
  doi          = {10.1007/978-3-540-71528-3\_5},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/GeigerMT07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/ZimmerHKTW07,
  author       = {Christopher Zimmer and
                  Stephen Roderick Hines and
                  Prasad A. Kulkarni and
                  Gary S. Tyson and
                  David B. Whalley},
  editor       = {Taewhan Kim and
                  Pascal Sainrat and
                  Steven S. Lumetta and
                  Nacho Navarro},
  title        = {Facilitating compiler optimizations through the dynamic mapping of
                  alternate register structures},
  booktitle    = {Proceedings of the 2007 International Conference on Compilers, Architecture,
                  and Synthesis for Embedded Systems, {CASES} 2007, Salzburg, Austria,
                  September 30 - October 3, 2007},
  pages        = {165--169},
  publisher    = {{ACM}},
  year         = {2007},
  url          = {https://doi.org/10.1145/1289881.1289912},
  doi          = {10.1145/1289881.1289912},
  timestamp    = {Tue, 10 Dec 2019 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/cases/ZimmerHKTW07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cgo/KulkarniWT07,
  author       = {Prasad A. Kulkarni and
                  David B. Whalley and
                  Gary S. Tyson},
  title        = {Evaluating Heuristic Optimization Phase Order Search Algorithms},
  booktitle    = {Fifth International Symposium on Code Generation and Optimization
                  {(CGO} 2007), 11-14 March 2007, San Jose, California, {USA}},
  pages        = {157--169},
  publisher    = {{IEEE} Computer Society},
  year         = {2007},
  url          = {https://doi.org/10.1109/CGO.2007.9},
  doi          = {10.1109/CGO.2007.9},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/cgo/KulkarniWT07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/BhadauriaMST07,
  author       = {Major Bhadauria and
                  Sally A. McKee and
                  Karan Singh and
                  Gary S. Tyson},
  editor       = {Koen De Bosschere and
                  David R. Kaeli and
                  Per Stenstr{\"{o}}m and
                  David B. Whalley and
                  Theo Ungerer},
  title        = {Leveraging High Performance Data Cache Techniques to Save Power in
                  Embedded Systems},
  booktitle    = {High Performance Embedded Architectures and Compilers, Second International
                  Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {4367},
  pages        = {23--37},
  publisher    = {Springer},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-69338-3\_3},
  doi          = {10.1007/978-3-540-69338-3\_3},
  timestamp    = {Tue, 14 May 2019 10:00:51 +0200},
  biburl       = {https://dblp.org/rec/conf/hipeac/BhadauriaMST07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lctrts/HinesTW07,
  author       = {Stephen Roderick Hines and
                  Gary S. Tyson and
                  David B. Whalley},
  editor       = {Santosh Pande and
                  Zhiyuan Li},
  title        = {Addressing instruction fetch bottlenecks by using an instruction register
                  file},
  booktitle    = {Proceedings of the 2007 {ACM} {SIGPLAN/SIGBED} Conference on Languages,
                  Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California,
                  USA, June 13-15, 2007},
  pages        = {165--174},
  publisher    = {{ACM}},
  year         = {2007},
  url          = {https://doi.org/10.1145/1254766.1254800},
  doi          = {10.1145/1254766.1254800},
  timestamp    = {Sun, 02 Oct 2022 16:11:14 +0200},
  biburl       = {https://dblp.org/rec/conf/lctrts/HinesTW07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/HinesWT07,
  author       = {Stephen Hines and
                  David B. Whalley and
                  Gary S. Tyson},
  title        = {Guaranteeing Hits to Improve the Efficiency of a Small Instruction
                  Cache},
  booktitle    = {40th Annual {IEEE/ACM} International Symposium on Microarchitecture
                  {(MICRO-40} 2007), 1-5 December 2007, Chicago, Illinois, {USA}},
  pages        = {433--444},
  publisher    = {{IEEE} Computer Society},
  year         = {2007},
  url          = {https://doi.org/10.1109/MICRO.2007.28},
  doi          = {10.1109/MICRO.2007.28},
  timestamp    = {Tue, 31 May 2022 14:39:58 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/HinesWT07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/ChengT06,
  author       = {Allen C. Cheng and
                  Gary S. Tyson},
  title        = {High-quality {ISA} synthesis for low-power cache designs in embedded
                  microprocessors},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {50},
  number       = {2-3},
  pages        = {299--310},
  year         = {2006},
  url          = {https://doi.org/10.1147/rd.502.0299},
  doi          = {10.1147/RD.502.0299},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/ChengT06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/HinesWT06,
  author       = {Stephen Hines and
                  David B. Whalley and
                  Gary S. Tyson},
  editor       = {Seongsoo Hong and
                  Wayne H. Wolf and
                  Kriszti{\'{a}}n Flautner and
                  Taewhan Kim},
  title        = {Adapting compilation techniques to enhance the packing of instructions
                  into registers},
  booktitle    = {Proceedings of the 2006 International Conference on Compilers, Architecture,
                  and Synthesis for Embedded Systems, {CASES} 2006, Seoul, Korea, October
                  22-25, 2006},
  pages        = {43--53},
  publisher    = {{ACM}},
  year         = {2006},
  url          = {https://doi.org/10.1145/1176760.1176768},
  doi          = {10.1145/1176760.1176768},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/cases/HinesWT06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cgo/KulkarniWTD06,
  author       = {Prasad A. Kulkarni and
                  David B. Whalley and
                  Gary S. Tyson and
                  Jack W. Davidson},
  title        = {Exhaustive Optimization Phase Order Space Exploration},
  booktitle    = {Fourth {IEEE/ACM} International Symposium on Code Generation and Optimization
                  {(CGO} 2006), 26-29 March 2006, New York, New York, {USA}},
  pages        = {306--318},
  publisher    = {{IEEE} Computer Society},
  year         = {2006},
  url          = {https://doi.org/10.1109/CGO.2006.15},
  doi          = {10.1109/CGO.2006.15},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/cgo/KulkarniWTD06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lctrts/KreahlingHWT06,
  author       = {William C. Kreahling and
                  Stephen Hines and
                  David B. Whalley and
                  Gary S. Tyson},
  editor       = {Mary Jane Irwin and
                  Koen De Bosschere},
  title        = {Reducing the cost of conditional transfers of control by using comparison
                  specifications},
  booktitle    = {Proceedings of the 2006 {ACM} {SIGPLAN/SIGBED} Conference on Languages,
                  Compilers, and Tools for Embedded Systems (LCTES'06), Ottawa, Ontario,
                  Canada, June 14-16, 2006},
  pages        = {64--71},
  publisher    = {{ACM}},
  year         = {2006},
  url          = {https://doi.org/10.1145/1134650.1134661},
  doi          = {10.1145/1134650.1134661},
  timestamp    = {Fri, 25 Jun 2021 14:48:54 +0200},
  biburl       = {https://dblp.org/rec/conf/lctrts/KreahlingHWT06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lctrts/KulkarniWTD06,
  author       = {Prasad A. Kulkarni and
                  David B. Whalley and
                  Gary S. Tyson and
                  Jack W. Davidson},
  editor       = {Mary Jane Irwin and
                  Koen De Bosschere},
  title        = {In search of near-optimal optimization phase orderings},
  booktitle    = {Proceedings of the 2006 {ACM} {SIGPLAN/SIGBED} Conference on Languages,
                  Compilers, and Tools for Embedded Systems (LCTES'06), Ottawa, Ontario,
                  Canada, June 14-16, 2006},
  pages        = {83--92},
  publisher    = {{ACM}},
  year         = {2006},
  url          = {https://doi.org/10.1145/1134650.1134663},
  doi          = {10.1145/1134650.1134663},
  timestamp    = {Fri, 25 Jun 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/lctrts/KulkarniWTD06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ChengT05,
  author       = {Allen C. Cheng and
                  Gary S. Tyson},
  title        = {An Energy Efficient Instruction Set Synthesis Framework for Low Power
                  Embedded System Designs},
  journal      = {{IEEE} Trans. Computers},
  volume       = {54},
  number       = {6},
  pages        = {698--713},
  year         = {2005},
  url          = {https://doi.org/10.1109/TC.2005.89},
  doi          = {10.1109/TC.2005.89},
  timestamp    = {Sat, 20 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tc/ChengT05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cf/GeigerMT05,
  author       = {Michael J. Geiger and
                  Sally A. McKee and
                  Gary S. Tyson},
  editor       = {Nader Bagherzadeh and
                  Mateo Valero and
                  Alex Ram{\'{\i}}rez},
  title        = {Drowsy region-based caches: minimizing both dynamic and static power
                  dissipation},
  booktitle    = {Proceedings of the Second Conference on Computing Frontiers, 2005,
                  Ischia, Italy, May 4-6, 2005},
  pages        = {378--384},
  publisher    = {{ACM}},
  year         = {2005},
  url          = {https://doi.org/10.1145/1062261.1062322},
  doi          = {10.1145/1062261.1062322},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/cf/GeigerMT05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/GeigerMT05,
  author       = {Michael J. Geiger and
                  Sally A. McKee and
                  Gary S. Tyson},
  editor       = {Thomas M. Conte and
                  Nacho Navarro and
                  Wen{-}mei W. Hwu and
                  Mateo Valero and
                  Theo Ungerer},
  title        = {Beyond Basic Region Caching: Specializing Cache Structures for High
                  Performance and Energy Conservation},
  booktitle    = {High Performance Embedded Architectures and Compilers, First International
                  Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {3793},
  pages        = {102--115},
  publisher    = {Springer},
  year         = {2005},
  url          = {https://doi.org/10.1007/11587514\_8},
  doi          = {10.1007/11587514\_8},
  timestamp    = {Tue, 14 May 2019 10:00:51 +0200},
  biburl       = {https://dblp.org/rec/conf/hipeac/GeigerMT05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/HinesGTW05,
  author       = {Stephen Hines and
                  Joshua Green and
                  Gary S. Tyson and
                  David B. Whalley},
  title        = {Improving Program Efficiency by Packing Instructions into Registers},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {260--271},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.32},
  doi          = {10.1109/ISCA.2005.32},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/HinesGTW05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/ChengTM05,
  author       = {Allen C. Cheng and
                  Gary S. Tyson and
                  Trevor N. Mudge},
  title        = {PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application
                  Specific Instruction Set Synthesis},
  booktitle    = {{IEEE} International Symposium on Performance Analysis of Systems
                  and Software, {ISPASS} 2005, March 20-22, 2005, Austin, Texas, USA,
                  Proceedings},
  pages        = {32--41},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISPASS.2005.1430557},
  doi          = {10.1109/ISPASS.2005.1430557},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ispass/ChengTM05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/HinesTW05,
  author       = {Stephen Hines and
                  Gary S. Tyson and
                  David B. Whalley},
  title        = {Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows},
  booktitle    = {38th Annual {IEEE/ACM} International Symposium on Microarchitecture
                  {(MICRO-38} 2005), 12-16 November 2005, Barcelona, Spain},
  pages        = {19--29},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/MICRO.2005.27},
  doi          = {10.1109/MICRO.2005.27},
  timestamp    = {Tue, 31 May 2022 14:39:58 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/HinesTW05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/SrinivasanDT04,
  author       = {Viji Srinivasan and
                  Edward S. Davidson and
                  Gary S. Tyson},
  title        = {A Prefetch Taxonomy},
  journal      = {{IEEE} Trans. Computers},
  volume       = {53},
  number       = {2},
  pages        = {126--140},
  year         = {2004},
  url          = {https://doi.org/10.1109/TC.2004.1261824},
  doi          = {10.1109/TC.2004.1261824},
  timestamp    = {Sat, 20 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tc/SrinivasanDT04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChengTM04,
  author       = {Allen C. Cheng and
                  Gary S. Tyson and
                  Trevor N. Mudge},
  editor       = {Sharad Malik and
                  Limor Fix and
                  Andrew B. Kahng},
  title        = {{FITS:} framework-based instruction-set tuning synthesis for embedded
                  application specific processors},
  booktitle    = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
                  San Diego, CA, USA, June 7-11, 2004},
  pages        = {920--923},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/996566.996810},
  doi          = {10.1145/996566.996810},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dac/ChengTM04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jilp/LeeTF01,
  author       = {Hsien{-}Hsin S. Lee and
                  Gary S. Tyson and
                  Matthew K. Farrens},
  title        = {Improving Bandwidth Utilization using Eager Writeback},
  journal      = {J. Instr. Level Parallelism},
  volume       = {3},
  year         = {2001},
  url          = {http://www.jilp.org/vol3/lee-jilp.pdf},
  timestamp    = {Mon, 11 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jilp/LeeTF01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/LeeSNT01,
  author       = {Hsien{-}Hsin S. Lee and
                  Mikhail Smelyanskiy and
                  Chris J. Newburn and
                  Gary S. Tyson},
  title        = {Stack Value File: Custom Microarchitecture for the Stack},
  booktitle    = {Proceedings of the Seventh International Symposium on High-Performance
                  Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24,
                  2001},
  pages        = {5--14},
  publisher    = {{IEEE} Computer Society},
  year         = {2001},
  url          = {https://doi.org/10.1109/HPCA.2001.903247},
  doi          = {10.1109/HPCA.2001.903247},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hpca/LeeSNT01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/SrinivasanDTCP01,
  author       = {Viji Srinivasan and
                  Edward S. Davidson and
                  Gary S. Tyson and
                  Mark J. Charney and
                  Thomas R. Puzak},
  title        = {Branch History Guided Instruction Prefetching},
  booktitle    = {Proceedings of the Seventh International Symposium on High-Performance
                  Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24,
                  2001},
  pages        = {291--300},
  publisher    = {{IEEE} Computer Society},
  year         = {2001},
  url          = {https://doi.org/10.1109/HPCA.2001.903271},
  doi          = {10.1109/HPCA.2001.903271},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hpca/SrinivasanDTCP01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/TamVTD01,
  author       = {Edward S. Tam and
                  Stevan A. Vlaovic and
                  Gary S. Tyson and
                  Edward S. Davidson},
  title        = {Allocation by Conflict: {A} Simple Effective Multilateral Cache Management
                  Scheme},
  booktitle    = {19th International Conference on Computer Design {(ICCD} 2001), {VLSI}
                  in Computers and Processors, 23-26 September 2001, Austin, TX, USA,
                  Proceedings},
  pages        = {133--141},
  publisher    = {{IEEE} Computer Society},
  year         = {2001},
  url          = {https://doi.org/10.1109/ICCD.2001.955015},
  doi          = {10.1109/ICCD.2001.955015},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iccd/TamVTD01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/SmelyanskiyTD00,
  author       = {Mikhail Smelyanskiy and
                  Gary S. Tyson and
                  Edward S. Davidson},
  title        = {Register Queues: {A} New Hardware/Software Approach to Efficient Software
                  Pipelining},
  booktitle    = {Proceedings of the 2000 International Conference on Parallel Architectures
                  and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania,
                  USA, October 15-19, 2000},
  pages        = {3--12},
  publisher    = {{IEEE} Computer Society},
  year         = {2000},
  url          = {https://doi.org/10.1109/PACT.2000.888255},
  doi          = {10.1109/PACT.2000.888255},
  timestamp    = {Tue, 31 May 2022 13:36:12 +0200},
  biburl       = {https://dblp.org/rec/conf/IEEEpact/SmelyanskiyTD00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/LeeT00,
  author       = {Hsien{-}Hsin S. Lee and
                  Gary S. Tyson},
  title        = {Region-based caching: an energy-delay efficient memory architecture
                  for embedded processors},
  booktitle    = {Proceedings of the 2000 International Conference on Compilers, Architectures
                  and Synthesis for Embedded Systems, {CASES} 2000, San Jose, California,
                  USA, November 7-18, 2000},
  pages        = {120--127},
  publisher    = {{ACM}},
  year         = {2000},
  url          = {https://doi.org/10.1145/354880.354898},
  doi          = {10.1145/354880.354898},
  timestamp    = {Tue, 06 Nov 2018 11:07:42 +0100},
  biburl       = {https://dblp.org/rec/conf/cases/LeeT00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/LeeWT00,
  author       = {Hsien{-}Hsin S. Lee and
                  Youfeng Wu and
                  Gary S. Tyson},
  title        = {Quantifying instruction-level parallelism limits on an {EPIC} architecture},
  booktitle    = {2000 {IEEE} International Symposium on Performance Analysis of Systems
                  and Software, April 24-35, 2000, Austin, Texas, USA, Proceedings},
  pages        = {21--27},
  publisher    = {{IEEE} Computer Society},
  year         = {2000},
  url          = {https://doi.org/10.1109/ISPASS.2000.842276},
  doi          = {10.1109/ISPASS.2000.842276},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/ispass/LeeWT00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/AnnavaramTD00,
  author       = {Murali Annavaram and
                  Gary S. Tyson and
                  Edward S. Davidson},
  title        = {Instruction overhead and data locality effects in superscalar processors},
  booktitle    = {2000 {IEEE} International Symposium on Performance Analysis of Systems
                  and Software, April 24-35, 2000, Austin, Texas, USA, Proceedings},
  pages        = {95--100},
  publisher    = {{IEEE} Computer Society},
  year         = {2000},
  url          = {https://doi.org/10.1109/ISPASS.2000.842287},
  doi          = {10.1109/ISPASS.2000.842287},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ispass/AnnavaramTD00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/LeeTF00,
  author       = {Hsien{-}Hsin S. Lee and
                  Gary S. Tyson and
                  Matthew K. Farrens},
  editor       = {Andrew Wolfe and
                  Michael S. Schlansker},
  title        = {Eager writeback - a technique for improving bandwidth utilization},
  booktitle    = {Proceedings of the 33rd Annual {IEEE/ACM} International Symposium
                  on Microarchitecture, {MICRO} 33, Monterey, California, USA, December
                  10-13, 2000},
  pages        = {11--21},
  publisher    = {{ACM/IEEE} Computer Society},
  year         = {2000},
  url          = {https://doi.org/10.1109/MICRO.2000.898054},
  doi          = {10.1109/MICRO.2000.898054},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/LeeTF00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/VlaovicDT00,
  author       = {Stevan A. Vlaovic and
                  Edward S. Davidson and
                  Gary S. Tyson},
  editor       = {Andrew Wolfe and
                  Michael S. Schlansker},
  title        = {Improving {BTB} performance in the presence of DLLs},
  booktitle    = {Proceedings of the 33rd Annual {IEEE/ACM} International Symposium
                  on Microarchitecture, {MICRO} 33, Monterey, California, USA, December
                  10-13, 2000},
  pages        = {77--86},
  publisher    = {{ACM/IEEE} Computer Society},
  year         = {2000},
  url          = {https://doi.org/10.1109/MICRO.2000.898060},
  doi          = {10.1109/MICRO.2000.898060},
  timestamp    = {Tue, 31 May 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/VlaovicDT00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/TysonA99,
  author       = {Gary S. Tyson and
                  Todd M. Austin},
  title        = {Memory Renaming: Fast, Early and Accurate Processing of Memory Communication},
  journal      = {Int. J. Parallel Program.},
  volume       = {27},
  number       = {5},
  pages        = {357--380},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1018734923512},
  doi          = {10.1023/A:1018734923512},
  timestamp    = {Wed, 01 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijpp/TysonA99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jilp/PostiffTM99,
  author       = {Matt Postiff and
                  Gary S. Tyson and
                  Trevor N. Mudge},
  title        = {Performance Limits of Trace Caches},
  journal      = {J. Instr. Level Parallelism},
  volume       = {1},
  year         = {1999},
  url          = {http://www.jilp.org/vol1/v1paper5.pdf},
  timestamp    = {Mon, 11 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jilp/PostiffTM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/PostiffGTM99,
  author       = {Matthew A. Postiff and
                  David A. Greene and
                  Gary S. Tyson and
                  Trevor N. Mudge},
  title        = {The limits of instruction level parallelism in {SPEC95} applications},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {27},
  number       = {1},
  pages        = {31--34},
  year         = {1999},
  url          = {https://doi.org/10.1145/309758.309771},
  doi          = {10.1145/309758.309771},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/PostiffGTM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/FlautnerTM99,
  author       = {Kriszti{\'{a}}n Flautner and
                  Gary S. Tyson and
                  Trevor N. Mudge},
  title        = {A high level simulator integrated with the Mirv compiler},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {27},
  number       = {1},
  pages        = {43--46},
  year         = {1999},
  url          = {https://doi.org/10.1145/309758.309778},
  doi          = {10.1145/309758.309778},
  timestamp    = {Sat, 21 Oct 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/FlautnerTM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/TamRSTD99,
  author       = {Edward S. Tam and
                  Jude A. Rivers and
                  Vijayalakshmi Srinivasan and
                  Gary S. Tyson and
                  Edward S. Davidson},
  title        = {Active Management of Data Caches by Exploiting Reuse Information},
  journal      = {{IEEE} Trans. Computers},
  volume       = {48},
  number       = {11},
  pages        = {1244--1259},
  year         = {1999},
  url          = {https://doi.org/10.1109/12.811113},
  doi          = {10.1109/12.811113},
  timestamp    = {Sat, 20 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tc/TamRSTD99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ics/ReinmanCTTA99,
  author       = {Glenn Reinman and
                  Brad Calder and
                  Dean M. Tullsen and
                  Gary S. Tyson and
                  Todd M. Austin},
  editor       = {Theodore S. Papatheodorou and
                  Mateo Valero and
                  Constantine D. Polychronopoulos and
                  Yoichi Muraoka and
                  Jes{\'{u}}s Labarta},
  title        = {Classifying load and store instructions for memory renaming},
  booktitle    = {Proceedings of the 13th international conference on Supercomputing,
                  {ICS} 1999, Rhodes, Greece, June 20-25, 1999},
  pages        = {399--407},
  publisher    = {{ACM}},
  year         = {1999},
  url          = {https://doi.org/10.1145/305138.305218},
  doi          = {10.1145/305138.305218},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/ics/ReinmanCTTA99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/TamRSTD98,
  author       = {Edward S. Tam and
                  Jude A. Rivers and
                  Vijayalakshmi Srinivasan and
                  Gary S. Tyson and
                  Edward S. Davidson},
  title        = {Evaluating the performance of active cache management schemes},
  booktitle    = {International Conference on Computer Design: {VLSI} in Computers and
                  Processors, {ICCD} 1998, Proceedings, 5-7 October, 1998, Austin, TX,
                  {USA}},
  pages        = {368--375},
  publisher    = {{IEEE} Computer Society},
  year         = {1998},
  url          = {https://doi.org/10.1109/ICCD.1998.727076},
  doi          = {10.1109/ICCD.1998.727076},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iccd/TamRSTD98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ics/RiversTTDF98,
  author       = {Jude A. Rivers and
                  Edward S. Tam and
                  Gary S. Tyson and
                  Edward S. Davidson and
                  Matthew K. Farrens},
  editor       = {Greg K. Egan and
                  Richard P. Brent and
                  Dennis Gannon},
  title        = {Utilizing Reuse Information in Data Cache Management},
  booktitle    = {Proceedings of the 12th international conference on Supercomputing,
                  {ICS} 1998, Melbourne, Australia, July 13-17, 1998},
  pages        = {449--456},
  publisher    = {{ACM}},
  year         = {1998},
  url          = {https://doi.org/10.1145/277830.277941},
  doi          = {10.1145/277830.277941},
  timestamp    = {Tue, 06 Nov 2018 11:07:02 +0100},
  biburl       = {https://dblp.org/rec/conf/ics/RiversTTDF98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mascots/TamRTD98,
  author       = {Edward S. Tam and
                  Jude A. Rivers and
                  Gary S. Tyson and
                  Edward S. Davidson},
  title        = {mlcache: {A} Flexible Multi-Lateral Cache Simulator},
  booktitle    = {{MASCOTS} 1998, Proceedings of the Sixth International Symposium on
                  Modeling, Analysis and Simulation of Computer and Telecommunication
                  Systems, 19-24 July, 1998, Montreal, Canada},
  pages        = {19--26},
  publisher    = {{IEEE} Computer Society},
  year         = {1998},
  url          = {https://doi.org/10.1109/MASCOT.1998.693670},
  doi          = {10.1109/MASCOT.1998.693670},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/mascots/TamRTD98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/KimT98,
  author       = {Sangwook P. Kim and
                  Gary S. Tyson},
  editor       = {James O. Bondi and
                  Jim Smith},
  title        = {Analyzing the Working Set Characteristics of Branch Execution},
  booktitle    = {Proceedings of the 31st Annual {IEEE/ACM} International Symposium
                  on Microarchitecture, {MICRO} 31, Dallas, Texas, USA, November 30
                  - December 2, 1998},
  pages        = {49--58},
  publisher    = {{ACM/IEEE} Computer Society},
  year         = {1998},
  url          = {https://doi.org/10.1109/MICRO.1998.742768},
  doi          = {10.1109/MICRO.1998.742768},
  timestamp    = {Tue, 31 May 2022 14:39:58 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/KimT98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wcae/TysonRM98,
  author       = {Gary S. Tyson and
                  Steven K. Reinhardt and
                  Trevor N. Mudge},
  title        = {Computer architecture instruction at the University of Michigan},
  booktitle    = {Proceedings of the 1998 workshop on Computer architecture education,
                  WCAE@ISCA 1998, Barcelona, Spain, June 1998},
  pages        = {2},
  publisher    = {{ACM}},
  year         = {1998},
  url          = {https://doi.org/10.1145/1275182.1275184},
  doi          = {10.1145/1275182.1275184},
  timestamp    = {Tue, 06 Nov 2018 16:57:55 +0100},
  biburl       = {https://dblp.org/rec/conf/wcae/TysonRM98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/TysonFMP97,
  author       = {Gary S. Tyson and
                  Matthew K. Farrens and
                  John Matthews and
                  Andrew R. Pleszkun},
  title        = {Managing data caches using selective cache line replacement},
  journal      = {Int. J. Parallel Program.},
  volume       = {25},
  number       = {3},
  pages        = {213--242},
  year         = {1997},
  url          = {https://doi.org/10.1007/BF02700036},
  doi          = {10.1007/BF02700036},
  timestamp    = {Wed, 01 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijpp/TysonFMP97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/RiversTDA97,
  author       = {Jude A. Rivers and
                  Gary S. Tyson and
                  Edward S. Davidson and
                  Todd M. Austin},
  editor       = {Mark Smotherman and
                  Tom Conte},
  title        = {On High-Bandwidth Data Cache Design for Multi-Issue Processors},
  booktitle    = {Proceedings of the Thirtieth Annual {IEEE/ACM} International Symposium
                  on Microarchitecture, {MICRO} 30, Research Triangle Park, North Carolina,
                  USA, December 1-3, 1997},
  pages        = {46--56},
  publisher    = {{ACM/IEEE} Computer Society},
  year         = {1997},
  url          = {https://doi.org/10.1109/MICRO.1997.645796},
  doi          = {10.1109/MICRO.1997.645796},
  timestamp    = {Tue, 31 May 2022 14:39:58 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/RiversTDA97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/TysonA97,
  author       = {Gary S. Tyson and
                  Todd M. Austin},
  editor       = {Mark Smotherman and
                  Tom Conte},
  title        = {Improving the Accuracy and Performance of Memory Communication Through
                  Renaming},
  booktitle    = {Proceedings of the Thirtieth Annual {IEEE/ACM} International Symposium
                  on Microarchitecture, {MICRO} 30, Research Triangle Park, North Carolina,
                  USA, December 1-3, 1997},
  pages        = {218--227},
  publisher    = {{ACM/IEEE} Computer Society},
  year         = {1997},
  url          = {https://doi.org/10.1109/MICRO.1997.645812},
  doi          = {10.1109/MICRO.1997.645812},
  timestamp    = {Tue, 31 May 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/TysonA97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/TysonF96,
  author       = {Gary S. Tyson and
                  Matthew K. Farrens},
  title        = {Evaluating the Effects of Predicated Execution on Branch Prediction},
  journal      = {Int. J. Parallel Program.},
  volume       = {24},
  number       = {2},
  pages        = {159--186},
  year         = {1996},
  url          = {https://doi.org/10.1007/bf03356746},
  doi          = {10.1007/BF03356746},
  timestamp    = {Fri, 10 Jun 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijpp/TysonF96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/TysonFMP95,
  author       = {Gary S. Tyson and
                  Matthew K. Farrens and
                  John Matthews and
                  Andrew R. Pleszkun},
  editor       = {Trevor N. Mudge and
                  Kemal Ebcioglu},
  title        = {A modified approach to data cache management},
  booktitle    = {Proceedings of the 28th Annual International Symposium on Microarchitecture,
                  Ann Arbor, Michigan, USA, November 29 - December 1, 1995},
  pages        = {93--103},
  publisher    = {{ACM} / {IEEE} Computer Society},
  year         = {1995},
  url          = {https://doi.org/10.1109/MICRO.1995.476816},
  doi          = {10.1109/MICRO.1995.476816},
  timestamp    = {Tue, 31 May 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/TysonFMP95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/TysonF94,
  author       = {Gary S. Tyson and
                  Matthew K. Farrens},
  title        = {Code scheduling for multiple instruction stream architectures},
  journal      = {Int. J. Parallel Program.},
  volume       = {22},
  number       = {3},
  pages        = {243--272},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF02577734},
  doi          = {10.1007/BF02577734},
  timestamp    = {Wed, 01 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijpp/TysonF94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/FarrensTP94,
  author       = {Matthew K. Farrens and
                  Gary S. Tyson and
                  Andrew R. Pleszkun},
  editor       = {David A. Patterson},
  title        = {A Study of Single-Chip Processor/Cache Organizations for Large Numbers
                  of Transistors},
  booktitle    = {Proceedings of the 21st Annual International Symposium on Computer
                  Architecture. Chicago, IL, USA, April 1994},
  pages        = {338--347},
  publisher    = {{IEEE} Computer Society},
  year         = {1994},
  url          = {https://doi.org/10.1109/ISCA.1994.288137},
  doi          = {10.1109/ISCA.1994.288137},
  timestamp    = {Thu, 13 Apr 2023 19:55:42 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/FarrensTP94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/Tyson94,
  author       = {Gary S. Tyson},
  editor       = {Hans Mulder and
                  Matthew K. Farrens},
  title        = {The effects of predicated execution on branch prediction},
  booktitle    = {Proceedings of the 27th Annual International Symposium on Microarchitecture,
                  San Jose, California, USA, November 30 - December 2, 1994},
  pages        = {196--206},
  publisher    = {{ACM} / {IEEE} Computer Society},
  year         = {1994},
  url          = {https://doi.org/10.1109/MICRO.1994.717459},
  doi          = {10.1109/MICRO.1994.717459},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/Tyson94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/TysonF93,
  author       = {Gary S. Tyson and
                  Matthew K. Farrens},
  editor       = {Andrew Wolfe and
                  William H. Mangione{-}Smith},
  title        = {Techniques for extracting instruction level parallelism on {MIMD}
                  architectures},
  booktitle    = {Proceedings of the 26th Annual International Symposium on Microarchitecture,
                  Austin, Texas, USA, November 1993},
  pages        = {128--137},
  publisher    = {{ACM} / {IEEE} Computer Society},
  year         = {1993},
  url          = {https://doi.org/10.1109/MICRO.1993.282749},
  doi          = {10.1109/MICRO.1993.282749},
  timestamp    = {Tue, 31 May 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/TysonF93.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/FarrensPFNT92,
  author       = {Matthew K. Farrens and
                  Arvin Park and
                  Rob Fanfelle and
                  Pius Ng and
                  Gary S. Tyson},
  editor       = {Allan Gottlieb},
  title        = {A partitioned translation lookaside buffer approach to reducing address
                  bandwith},
  booktitle    = {Proceedings of the 19th Annual International Symposium on Computer
                  Architecture. Gold Coast, Australia, May 1992},
  pages        = {435},
  publisher    = {{ACM}},
  year         = {1992},
  url          = {https://doi.org/10.1145/146628.140546},
  doi          = {10.1145/146628.140546},
  timestamp    = {Fri, 09 Jul 2021 15:51:20 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/FarrensPFNT92.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/TysonFP92,
  author       = {Gary S. Tyson and
                  Matthew K. Farrens and
                  Andrew R. Pleszkun},
  editor       = {Wen{-}mei W. Hwu},
  title        = {{MISC:} a Multiple Instruction Stream Computer},
  booktitle    = {Proceedings of the 25th Annual International Symposium on Microarchitecture,
                  Portland, Oregon, USA, November 1992},
  pages        = {193--196},
  publisher    = {{ACM} / {IEEE} Computer Society},
  year         = {1992},
  url          = {https://doi.org/10.1109/MICRO.1992.697016},
  doi          = {10.1109/MICRO.1992.697016},
  timestamp    = {Tue, 31 May 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/TysonFP92.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/FarrensPT92,
  author       = {Matthew K. Farrens and
                  Arvin Park and
                  Gary S. Tyson},
  editor       = {Wen{-}mei W. Hwu},
  title        = {Modifying {VM} hardware to reduce address pin requirements},
  booktitle    = {Proceedings of the 25th Annual International Symposium on Microarchitecture,
                  Portland, Oregon, USA, November 1992},
  pages        = {210--213},
  publisher    = {{ACM} / {IEEE} Computer Society},
  year         = {1992},
  url          = {https://doi.org/10.1109/MICRO.1992.697020},
  doi          = {10.1109/MICRO.1992.697020},
  timestamp    = {Tue, 31 May 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/FarrensPT92.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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