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ORCIDBibTeX records: Allen C.-H. Wu
@article{DBLP:journals/cee/SunWH21,
author = {Chin{-}Yu Sun and
Allen C.{-}H. Wu and
TingTing Hwang},
title = {A novel privacy-preserving deep learning scheme without a cryptography
component},
journal = {Comput. Electr. Eng.},
volume = {94},
pages = {107325},
year = {2021},
url = {https://doi.org/10.1016/j.compeleceng.2021.107325},
doi = {10.1016/J.COMPELECENG.2021.107325},
timestamp = {Tue, 05 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cee/SunWH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChenWH21,
author = {Yen{-}Hao Chen and
Allen C.{-}H. Wu and
TingTing Hwang},
title = {A Dynamic Link-latency Aware Cache Replacement Policy {(DLRP)}},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {210--215},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431420},
doi = {10.1145/3394885.3431420},
timestamp = {Mon, 03 May 2021 16:42:27 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChenWH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/HoCWH19,
author = {Pei{-}An Ho and
Yen{-}Hao Chen and
Allen C.{-}H. Wu and
TingTing Hwang},
title = {Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs},
booktitle = {32nd {IEEE} International System-on-Chip Conference, {SOCC} 2019,
Singapore, September 3-6, 2019},
pages = {236--241},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SOCC46988.2019.1570544200},
doi = {10.1109/SOCC46988.2019.1570544200},
timestamp = {Tue, 19 May 2020 13:56:11 +0200},
biburl = {https://dblp.org/rec/conf/socc/HoCWH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/ChenHCWH19,
author = {Yen{-}Hao Chen and
Po{-}Chen Huang and
Fu{-}Wei Chen and
Allen C.{-}H. Wu and
TingTing Hwang},
title = {Crosstalk-aware TSV-buffer Insertion in 3D {IC}},
booktitle = {32nd {IEEE} International System-on-Chip Conference, {SOCC} 2019,
Singapore, September 3-6, 2019},
pages = {400--405},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SOCC46988.2019.1570539111},
doi = {10.1109/SOCC46988.2019.1570539111},
timestamp = {Tue, 19 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/ChenHCWH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1908-07701,
author = {Chin{-}Yu Sun and
Allen C.{-}H. Wu and
TingTing Hwang},
title = {A Novel Privacy-Preserving Deep Learning Scheme without Using Cryptography
Component},
journal = {CoRR},
volume = {abs/1908.07701},
year = {2019},
url = {http://arxiv.org/abs/1908.07701},
eprinttype = {arXiv},
eprint = {1908.07701},
timestamp = {Mon, 26 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1908-07701.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenTLWH17,
author = {Yen{-}Hao Chen and
Yi{-}Lun Tang and
Yi{-}Yu Liu and
Allen C.{-}H. Wu and
TingTing Hwang},
title = {A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling
Mechanism for Reliability Enhancements},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {820--832},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2614993},
doi = {10.1109/TVLSI.2016.2614993},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenTLWH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChenTLWH16,
author = {Yen{-}Hao Chen and
Yi{-}Lun Tang and
Yi{-}Yu Liu and
Allen C.{-}H. Wu and
TingTing Hwang},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {A novel cache-utilization based dynamic voltage frequency scaling
{(DVFS)} mechanism for reliability enhancements},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {79--84},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459284/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/ChenTLWH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/siggraph/LyuHCLWW15,
author = {Ruimin Lyu and
Haojie Hao and
Wei Chen and
Yuan Liu and
Feng Wang and
Allen C.{-}H. Wu},
title = {Elastylus: flexible haptic painting stylus},
booktitle = {{SIGGRAPH} Asia 2015 Emerging Technologies, Kobe, Japan, November
2-6, 2015},
pages = {10:1--10:3},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2818466.2818475},
doi = {10.1145/2818466.2818475},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/siggraph/LyuHCLWW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuoCHW07,
author = {Wu{-}An Kuo and
Yi{-}Ling Chiang and
TingTing Hwang and
Allen C.{-}H. Wu},
title = {Performance-Driven Crosstalk Elimination at Postcompiler Level-The
Case of Low-Crosstalk Op-Code Assignment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {564--573},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884861},
doi = {10.1109/TCAD.2006.884861},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuoCHW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/KuoHW06,
author = {Wu{-}An Kuo and
TingTing Hwang and
Allen C.{-}H. Wu},
title = {Decomposition of instruction decoders for low-power designs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {11},
number = {4},
pages = {880--889},
year = {2006},
url = {https://doi.org/10.1145/1179461.1179465},
doi = {10.1145/1179461.1179465},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/KuoHW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KuoHW06,
author = {Wu{-}An Kuo and
TingTing Hwang and
Allen C.{-}H. Wu},
title = {A power-driven multiplication instruction-set design method for ASIPs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {14},
number = {1},
pages = {81--85},
year = {2006},
url = {https://doi.org/10.1109/TVLSI.2005.863186},
doi = {10.1109/TVLSI.2005.863186},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KuoHW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KuoCHW06,
author = {Wu{-}An Kuo and
Yi{-}Ling Chiang and
TingTing Hwang and
Allen C.{-}H. Wu},
title = {Performance-driven crosstalk elimination at post-compiler level},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1693266},
doi = {10.1109/ISCAS.2006.1693266},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KuoCHW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KuoHW05,
author = {Wu{-}An Kuo and
TingTing Hwang and
Allen C.{-}H. Wu},
title = {A power-driven multiplication instruction-set design method for ASIPs},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {3311--3314},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465336},
doi = {10.1109/ISCAS.2005.1465336},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KuoHW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sip/WuLCLLW05,
author = {Bing{-}Fei Wu and
Chuan{-}Tsai Lin and
Chao{-}Jung Chen and
Tze{-}Chiuan Lai and
Hsueh{-}Lung Liao and
Allen C.{-}H. Wu},
editor = {Michael W. Marcellin},
title = {A fast lane and vehicle detection approach for autonomous vehicles},
booktitle = {Signal and Image Processing {(SIP} 2005), Proceedings of the {IASTED}
International Conference, August 15-17, 2005, Honolulu, HI, {USA}},
pages = {305--310},
publisher = {{IASTED/ACTA} Press},
year = {2005},
timestamp = {Thu, 25 Jan 2007 14:58:46 +0100},
biburl = {https://dblp.org/rec/conf/sip/WuLCLLW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KuoHW04,
author = {Wu{-}An Kuo and
TingTing Hwang and
Allen C.{-}H. Wu},
title = {Decomposition of Instruction Decoder for Low Power Design},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2004), 16-20 February 2004, Paris, France},
pages = {664--665},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DATE.2004.1268920},
doi = {10.1109/DATE.2004.1268920},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/KuoHW04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LoKWH03,
author = {Jennifer Y.{-}L. Lo and
Wu{-}An Kuo and
Allen C.{-}H. Wu and
TingTing Hwang},
title = {A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell
Designs},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {11102--11103},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10026},
doi = {10.1109/DATE.2003.10026},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/LoKWH03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChangKWH03,
author = {Alex C.{-}Y. Chang and
Wu{-}An Kuo and
Allen C.{-}H. Wu and
TingTing Hwang},
title = {{G-MAC:} An Application-Specific MAC/Co-Processor Synthesizer},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {11134--11135},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10153},
doi = {10.1109/DATE.2003.10153},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ChangKWH03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiaoSCW02,
author = {M.{-}J. Liao and
C.{-}F. Su and
Alex C.{-}Y. Chang and
Allen C.{-}H. Wu},
title = {A carry-select-adder optimization technique for high-performance Booth-encoded
Wallace-tree multipliers},
booktitle = {Proceedings of the 2002 International Symposium on Circuits and Systems,
{ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
pages = {81--84},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ISCAS.2002.1009782},
doi = {10.1109/ISCAS.2002.1009782},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LiaoSCW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KaoSW02,
author = {J. C.{-}Y. Kao and
C.{-}F. Su and
Allen C.{-}H. Wu},
title = {High-performance {FIR} generation based on a timing-driven architecture
and component selection method},
booktitle = {Proceedings of the 2002 International Symposium on Circuits and Systems,
{ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
pages = {759--762},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ISCAS.2002.1010568},
doi = {10.1109/ISCAS.2002.1010568},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KaoSW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KaoHW01,
author = {Peng{-}Cheng Kao and
Chih{-}Kuang Hsieh and
Allen C.{-}H. Wu},
editor = {Satoshi Goto},
title = {An {RTL} design-space exploration method for high-level applications},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {162--168},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370313},
doi = {10.1145/370155.370313},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KaoHW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/FangW00,
author = {Wen{-}Jong Fang and
Allen C.{-}H. Wu},
title = {Multiway {FPGA} partitioning by fully exploiting design hierarchy},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {1},
pages = {34--50},
year = {2000},
url = {https://doi.org/10.1145/329458.329463},
doi = {10.1145/329458.329463},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/FangW00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/HwangW00,
author = {Chi{-}Hong Hwang and
Allen C.{-}H. Wu},
title = {A predictive system shutdown method for energy saving of event-driven
computation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {2},
pages = {226--241},
year = {2000},
url = {https://doi.org/10.1145/335043.335046},
doi = {10.1145/335043.335046},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/HwangW00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuD00,
author = {Allen C.{-}H. Wu and
Nikil D. Dutt},
title = {Guest editorial 11th international symposium on system-level synthesis
and design (ISSS'98)},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {8},
number = {5},
pages = {469--471},
year = {2000},
url = {https://doi.org/10.1109/TVLSI.2000.894151},
doi = {10.1109/TVLSI.2000.894151},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WuD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GajskiWCMNB00,
author = {Daniel Gajski and
Allen C.{-}H. Wu and
Viraphol Chaiyakul and
Shojiro Mori and
Tom Nukiyama and
Pierre Bricaud},
title = {Embedded tutorial: essential issues for {IP} reuse},
booktitle = {Proceedings of {ASP-DAC} 2000, Asia and South Pacific Design Automation
Conference 2000, Yokohama, Japan},
pages = {37--42},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/368434.368504},
doi = {10.1145/368434.368504},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/GajskiWCMNB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KuoW00,
author = {Chien{-}Chu Kuo and
Allen C.{-}H. Wu},
editor = {Ellen Sentovich},
title = {Delay Budgeting for a Timing-Closure-Driven Design Method},
booktitle = {Proceedings of the 2000 {IEEE/ACM} International Conference on Computer-Aided
Design, 2000, San Jose, California, USA, November 5-9, 2000},
pages = {202--207},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCAD.2000.896475},
doi = {10.1109/ICCAD.2000.896475},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/KuoW00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuWL99,
author = {Hsiao{-}Pin Su and
Allen C.{-}H. Wu and
Youn{-}Long Lin},
title = {A timing-driven soft-macro placement and resynthesis method in interaction
with chip floorplanning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {475--483},
year = {1999},
url = {https://doi.org/10.1109/43.752930},
doi = {10.1109/43.752930},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuWL99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FangWC99,
author = {Wen{-}Jong Fang and
Allen C.{-}H. Wu and
Duan{-}Ping Chen},
title = {EmGen-a module generator for logic emulation applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {7},
number = {4},
pages = {488--492},
year = {1999},
url = {https://doi.org/10.1109/92.805756},
doi = {10.1109/92.805756},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FangWC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/FangKW99,
author = {Wen{-}Jong Fang and
Peng{-}Cheng Kao and
Allen C.{-}H. Wu},
title = {A Multi-Level {FPGA} Synthesis Method Supporting {HDL} Debugging for
Emulation-Based Designs},
booktitle = {Proceedings of the 1999 Conference on Asia South Pacific Design Automation,
Wanchai, Hong Kong, China, January 18-21, 1999},
pages = {351--354},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ASPDAC.1999.760031},
doi = {10.1109/ASPDAC.1999.760031},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/FangKW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SuWL99,
author = {Hsiao{-}Pin Su and
Allen C.{-}H. Wu and
Youn{-}Long Lin},
editor = {Mary Jane Irwin},
title = {A Timing-Driven Soft-Macro Resynthesis Method in Interaction with
Chip Floorplanning},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {262--267},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.309926},
doi = {10.1145/309847.309926},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SuWL99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HoW99,
author = {Kun{-}Ming Ho and
Allen C.{-}H. Wu},
editor = {Sinan Kaptanoglu and
Steve Trimberger},
title = {Module Generation of High Performance FPGA-Based Multipliers},
booktitle = {Proceedings of the 1999 {ACM/SIGDA} Seventh International Symposium
on Field Programmable Gate Arrays, {FPGA} 1999, Monterey, CA, USA,
February 21-23, 1999},
pages = {251},
publisher = {{ACM}},
year = {1999},
url = {https://doi.org/10.1145/296399.296520},
doi = {10.1145/296399.296520},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/HoW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/FangW98,
author = {Wen{-}Jong Fang and
Allen C.{-}H. Wu},
title = {Integrating {HDL} Synthesis and Partitioning for Multi-FPGA Designs},
journal = {{IEEE} Des. Test Comput.},
volume = {15},
number = {2},
pages = {65--72},
year = {1998},
url = {https://doi.org/10.1109/54.679209},
doi = {10.1109/54.679209},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/FangW98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/FangW98,
author = {Wen{-}Jong Fang and
Allen C.{-}H. Wu},
editor = {Basant R. Chawla and
Randal E. Bryant and
Jan M. Rabaey},
title = {Performance-Driven Multi-FPGA Partitioning Using Functional Clustering
and Replication},
booktitle = {Proceedings of the 35th Conference on Design Automation, Moscone center,
San Francico, California, USA, June 15-19, 1998},
pages = {283--286},
publisher = {{ACM} Press},
year = {1998},
url = {https://doi.org/10.1145/277044.277125},
doi = {10.1145/277044.277125},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/FangW98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/SuWL98,
author = {Hsiao{-}Pin Su and
Allen C.{-}H. Wu and
Youn{-}Long Lin},
editor = {Majid Sarrafzadeh},
title = {Performance-driven soft-macro clustering and placement by preserving
{HDL} design hierarchy},
booktitle = {Proceedings of the 1998 International Symposium on Physical Design,
{ISPD} 1998, Monterey, CA, USA, April 6-8, 1998},
pages = {12--17},
publisher = {{ACM}},
year = {1998},
url = {https://doi.org/10.1145/274535.274537},
doi = {10.1145/274535.274537},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/SuWL98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeW97,
author = {Yuh{-}Sheng Lee and
Allen C.{-}H. Wu},
title = {A performance and routability-driven router for FPGAs considering
path delays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {16},
number = {2},
pages = {179--185},
year = {1997},
url = {https://doi.org/10.1109/43.573832},
doi = {10.1109/43.573832},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeW97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FangW97,
author = {Wen{-}Jong Fang and
Allen C.{-}H. Wu},
title = {A hierarchical functional structuring and partitioning approach for
multiple-FPGA implementations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {16},
number = {10},
pages = {1188--1195},
year = {1997},
url = {https://doi.org/10.1109/43.662680},
doi = {10.1109/43.662680},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FangW97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LinHW97,
author = {Yann{-}Rue Lin and
Cheng{-}Tsung Hwang and
Allen C.{-}H. Wu},
title = {Scheduling techniques for variable voltage low power designs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {2},
number = {2},
pages = {81--97},
year = {1997},
url = {https://doi.org/10.1145/253052.253054},
doi = {10.1145/253052.253054},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LinHW97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Wu97,
author = {Allen C.{-}H. Wu},
title = {Datapath Optimization Using Layout Information: An Empirical Study},
journal = {{VLSI} Design},
volume = {5},
number = {2},
pages = {195--209},
year = {1997},
url = {https://doi.org/10.1155/1997/85473},
doi = {10.1155/1997/85473},
timestamp = {Sat, 05 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/Wu97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HwangW97,
author = {Chi{-}Hong Hwang and
Allen C.{-}H. Wu},
title = {An entropy measure for power estimation of Boolean functions},
booktitle = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
1997},
pages = {101--106},
publisher = {{IEEE}},
year = {1997},
url = {https://doi.org/10.1109/ASPDAC.1997.600067},
doi = {10.1109/ASPDAC.1997.600067},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/HwangW97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/IngHW97,
author = {Wei{-}Liang Ing and
Cheng{-}Tsung Hwang and
Allen C.{-}H. Wu},
title = {Evaluating cost-performance tradeoffs for system level applications},
booktitle = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
1997},
pages = {233--238},
publisher = {{IEEE}},
year = {1997},
url = {https://doi.org/10.1109/ASPDAC.1997.600128},
doi = {10.1109/ASPDAC.1997.600128},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/IngHW97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/FangWYL97,
author = {Wen{-}Jong Fang and
Allen C.{-}H. Wu and
Ti{-}Yen Yen and
Tsair{-}Chin Lin},
title = {DP-Gen: a datapath generator for multiple-FPGA applications},
booktitle = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
1997},
pages = {563--568},
publisher = {{IEEE}},
year = {1997},
url = {https://doi.org/10.1109/ASPDAC.1997.600337},
doi = {10.1109/ASPDAC.1997.600337},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/FangWYL97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/FangWY97,
author = {Wen{-}Jong Fang and
Allen C.{-}H. Wu and
Ti{-}Yen Yen},
editor = {Ellen J. Yoffa and
Giovanni De Micheli and
Jan M. Rabaey},
title = {A Real-Time {RTL} Engineering-Change Method Supporting On-Line Debugging
for Logic-Emulation Applications},
booktitle = {Proceedings of the 34st Conference on Design Automation, Anaheim,
California, USA, Anaheim Convention Center, June 9-13, 1997},
pages = {101--106},
publisher = {{ACM} Press},
year = {1997},
url = {https://doi.org/10.1145/266021.266043},
doi = {10.1145/266021.266043},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/FangWY97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/FangW97,
author = {Wen{-}Jong Fang and
Allen C.{-}H. Wu},
editor = {Ellen J. Yoffa and
Giovanni De Micheli and
Jan M. Rabaey},
title = {Multi-Way {FPGA} Partitioning by Fully Exploiting Design Hierarchy},
booktitle = {Proceedings of the 34st Conference on Design Automation, Anaheim,
California, USA, Anaheim Convention Center, June 9-13, 1997},
pages = {518--521},
publisher = {{ACM} Press},
year = {1997},
url = {https://doi.org/10.1145/266021.266270},
doi = {10.1145/266021.266270},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/FangW97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/FangWC97,
author = {Wen{-}Jong Fang and
Allen C.{-}H. Wu and
Duan{-}Ping Chen},
editor = {Carl Ebeling},
title = {Module Generation of Complex Macros for Logic-Emulation Applications},
booktitle = {Proceedings of the 1997 {ACM/SIGDA} Fifth International Symposium
on Field Programmable Gate Arrays, {FPGA} 1997, Monterey, CA, USA,
February 9-11, 1997},
pages = {69--75},
publisher = {{ACM}},
year = {1997},
url = {https://doi.org/10.1145/258305.258314},
doi = {10.1145/258305.258314},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/FangWC97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HwangW97,
author = {Chi{-}Hong Hwang and
Allen C.{-}H. Wu},
editor = {Ralph H. J. M. Otten and
Hiroto Yasuura},
title = {A predictive system shutdown method for energy saving of event-driven
computation},
booktitle = {Proceedings of the 1997 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1997, San Jose, CA, USA, November 9-13, 1997},
pages = {28--32},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1997},
url = {https://doi.org/10.1109/ICCAD.1997.643266},
doi = {10.1109/ICCAD.1997.643266},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HwangW97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/TsayFWL97,
author = {Yu{-}Wen Tsay and
Wen{-}Jong Fang and
Allen C.{-}H. Wu and
Youn{-}Long Lin},
editor = {Andrew B. Kahng and
Majid Sarrafzadeh},
title = {Preserving {HDL} synthesis hierarchy for cell placement},
booktitle = {Proceedings of the 1997 International Symposium on Physical Design,
{ISPD} 1997, Napa Valley, California, USA, April 14-16, 1997},
pages = {169--174},
publisher = {{ACM}},
year = {1997},
url = {https://doi.org/10.1145/267665.267709},
doi = {10.1145/267665.267709},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/TsayFWL97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/spe/LeeFW96,
author = {Tsing{-}Gen Lee and
Wen{-}Jong Fang and
Allen C.{-}H. Wu},
title = {The Design and Inplementation of a Cooperative Design-view Environment
for Interactive Partitioning Applications},
journal = {Softw. Pract. Exp.},
volume = {26},
number = {10},
pages = {1141--1160},
year = {1996},
url = {https://doi.org/10.1002/(SICI)1097-024X(199610)26:10\&\#60;1141::AID-SPE52\&\#62;3.0.CO;2-K},
doi = {10.1002/(SICI)1097-024X(199610)26:10\&\#60;1141::AID-SPE52\&\#62;3.0.CO;2-K},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/spe/LeeFW96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/FangW96,
author = {Wen{-}Jong Fang and
Allen C.{-}H. Wu},
editor = {Rob A. Rutenbar and
Ralph H. J. M. Otten},
title = {A hierarchical functional structuring and partitioning approach for
multiple-FPGA implementations},
booktitle = {Proceedings of the 1996 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1996, San Jose, CA, USA, November 10-14, 1996},
pages = {638--643},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1996},
url = {https://doi.org/10.1109/ICCAD.1996.571339},
doi = {10.1109/ICCAD.1996.571339},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/FangW96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/WuL95,
author = {Allen C.{-}H. Wu and
Youn{-}Long Lin},
title = {High-Level Synthesis -A Tutorial},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {78-D},
number = {3},
pages = {209--218},
year = {1995},
url = {http://search.ieice.org/bin/summary.php?id=e78-d\_3\_209},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/WuL95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenLWL95,
author = {Ching{-}Dong Chen and
Yuh{-}Sheng Lee and
Allen C.{-}H. Wu and
Youn{-}Long Lin},
title = {TRACER-fpga: a router for RAM-based FPGA's},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {14},
number = {3},
pages = {371--374},
year = {1995},
url = {https://doi.org/10.1109/43.365127},
doi = {10.1109/43.365127},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenLWL95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenTHWL95,
author = {Chau{-}Shen Chen and
Yu{-}Wen Tsay and
TingTing Hwang and
Allen C.{-}H. Wu and
Youn{-}Long Lin},
title = {Combining technology mapping and placement for delay-minimization
in {FPGA} designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {14},
number = {9},
pages = {1076--1084},
year = {1995},
url = {https://doi.org/10.1109/43.406709},
doi = {10.1109/43.406709},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenTHWL95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/FangWL95,
author = {Wen{-}Jong Fang and
Allen C.{-}H. Wu and
Tsing{-}Gen Lee},
editor = {Isao Shirakawa},
title = {{EMPAR:} an interactive synthesis environment for hardware emulations},
booktitle = {Proceedings of the 1995 Conference on Asia Pacific Design Automation,
Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995},
publisher = {{ACM}},
year = {1995},
url = {https://doi.org/10.1145/224818.224846},
doi = {10.1145/224818.224846},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/FangWL95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LeeW95,
author = {Yuh{-}Sheng Lee and
Allen C.{-}H. Wu},
editor = {Bryan Preas},
title = {A Performance and Routability Driven Router for FPGAs Considering
Path Delays},
booktitle = {Proceedings of the 32st Conference on Design Automation, San Francisco,
California, USA, Moscone Center, June 12-16, 1995},
pages = {557--561},
publisher = {{ACM} Press},
year = {1995},
url = {https://doi.org/10.1145/217474.217588},
doi = {10.1145/217474.217588},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LeeW95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeWLG94,
author = {Tsing{-}Fa Lee and
Allen C.{-}H. Wu and
Youn{-}Long Lin and
Daniel D. Gajski},
title = {A transformation-based method for loop folding},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {13},
number = {4},
pages = {439--450},
year = {1994},
url = {https://doi.org/10.1109/43.275354},
doi = {10.1109/43.275354},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeWLG94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/WuTWL94,
author = {Tsung{-}Yi Wu and
Tzu{-}Chieh Tien and
Allen C.{-}H. Wu and
Youn{-}Long Lin},
editor = {Robert Werner},
title = {A Synthesis Method for Mixed Synchronous / Asynchronous Behavior},
booktitle = {{EDAC} - The European Conference on Design Automation, {ETC} - European
Test Conference, {EUROASIC} - The European Event in {ASIC} Design,
Proceedings, February 28 - March 3, 1994, Paris, France},
pages = {277--281},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/EDTC.1994.326864},
doi = {10.1109/EDTC.1994.326864},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/WuTWL94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/WangWHWL94,
author = {Kuo{-}Hua Wang and
Wen{-}Sing Wang and
TingTing Hwang and
Allen C.{-}H. Wu and
Youn{-}Long Lin},
title = {State Assignment for Power and Area Minimization},
booktitle = {Proceedings 1994 {IEEE} International Conference on Computer Design:
{VLSI} in Computer {\&} Processors, {ICCD} '94, Cambridge, MA,
USA, October 10-12, 1994},
pages = {250--254},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/ICCD.1994.331899},
doi = {10.1109/ICCD.1994.331899},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/WangWHWL94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChenTHWL93,
author = {Chau{-}Shen Chen and
Yu{-}Wen Tsay and
TingTing Hwang and
Allen C.{-}H. Wu and
Youn{-}Long Lin},
editor = {Michael R. Lightner and
Jochen A. G. Jess},
title = {Combining technology mapping and placement for delay-optimization
in {FPGA} designs},
booktitle = {Proceedings of the 1993 {IEEE/ACM} International Conference on Computer-Aided
Design, 1993, Santa Clara, California, USA, November 7-11, 1993},
pages = {123--127},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1993},
url = {https://doi.org/10.1109/ICCAD.1993.580042},
doi = {10.1109/ICCAD.1993.580042},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ChenTHWL93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/sp/GajskiDWL92,
author = {Daniel D. Gajski and
Nikil D. Dutt and
Allen C.{-}H. Wu},
title = {Youn-Long Steve Lin},
publisher = {Springer},
year = {1992},
url = {https://doi.org/10.1007/978-1-4615-3636-9},
doi = {10.1007/978-1-4615-3636-9},
isbn = {978-1-4613-6617-1},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/sp/GajskiDWL92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LarmoreGW92,
author = {Lawrence L. Larmore and
Daniel D. Gajski and
Allen C.{-}H. Wu},
title = {Layout placement for sliced architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {11},
number = {1},
pages = {102--114},
year = {1992},
url = {https://doi.org/10.1109/43.108623},
doi = {10.1109/43.108623},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LarmoreGW92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuG92,
author = {Allen C.{-}H. Wu and
Daniel D. Gajski},
title = {Partitioning algorithms for layout synthesis from register-transfer
netlists},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {11},
number = {4},
pages = {453--463},
year = {1992},
url = {https://doi.org/10.1109/43.125093},
doi = {10.1109/43.125093},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuG92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/ChaiyakulWG92,
author = {Viraphol Chaiyakul and
Allen C.{-}H. Wu and
Daniel D. Gajski},
editor = {Gerald Musgrave},
title = {Timing models for high-level synthesis},
booktitle = {Proceedings of the conference on European design automation, {EURO-DAC}
'92, Hamburg, Germany, September 7-10, 1992},
pages = {60--65},
publisher = {{IEEE} Computer Society Press},
year = {1992},
url = {https://doi.org/10.1109/EURDAC.1992.246264},
doi = {10.1109/EURDAC.1992.246264},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/ChaiyakulWG92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LeeWGL92,
author = {Tsing{-}Fa Lee and
Allen C.{-}H. Wu and
Daniel Gajski and
Youn{-}Long Lin},
editor = {Louise Trevillyan and
Michael R. Lightner},
title = {An effective methodology for functional pipelining},
booktitle = {1992 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of
Technical Papers},
pages = {230--233},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1992},
url = {https://doi.org/10.1109/ICCAD.1992.279369},
doi = {10.1109/ICCAD.1992.279369},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LeeWGL92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WuHG92,
author = {Allen C.{-}H. Wu and
Tedd Hadley and
Daniel Gajski},
editor = {Louise Trevillyan and
Michael R. Lightner},
title = {An efficient multi-view design model for real-time interactive synthesis},
booktitle = {1992 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of
Technical Papers},
pages = {328--331},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1992},
url = {https://doi.org/10.1109/ICCAD.1992.279352},
doi = {10.1109/ICCAD.1992.279352},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/WuHG92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/RamachandranKGWC92,
author = {Champaka Ramachandran and
Fadi J. Kurdahi and
Daniel Gajski and
Allen C.{-}H. Wu and
Viraphol Chaiyakul},
editor = {Louise Trevillyan and
Michael R. Lightner},
title = {Accurate layout area and delay modeling for system level design},
booktitle = {1992 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of
Technical Papers},
pages = {355--361},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1992},
url = {https://doi.org/10.1109/ICCAD.1992.279347},
doi = {10.1109/ICCAD.1992.279347},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/RamachandranKGWC92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/WuG91,
author = {Allen C.{-}H. Wu and
Daniel D. Gajski},
editor = {Tony Ambler and
Jochen A. G. Jess and
Hugo De Man},
title = {Glue-logic partitioning for floorplans with a rectilinear datapath},
booktitle = {Proceedings of the conference on European design automation, EURO-DAC'91,
Amsterdam, The Netherlands, 1991},
pages = {162--166},
publisher = {{EEE} Computer Society},
year = {1991},
url = {http://dl.acm.org/citation.cfm?id=951549},
timestamp = {Tue, 17 Nov 2015 16:02:17 +0100},
biburl = {https://dblp.org/rec/conf/eurodac/WuG91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WuCG91,
author = {Allen C.{-}H. Wu and
Viraphol Chaiyakul and
Daniel Gajski},
title = {Layout-Area Models for High-Level Synthesis},
booktitle = {1991 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of
Technical Papers},
pages = {34--37},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/ICCAD.1991.185184},
doi = {10.1109/ICCAD.1991.185184},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/WuCG91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/WuZG90,
author = {Allen C.{-}H. Wu and
Nels Vander Zanden and
Daniel Gajski},
editor = {Gordon Adshead and
Jochen A. G. Jess},
title = {A new algorithm for transistor sizing in {CMOS} circuits},
booktitle = {European Design Automation Conference, {EURO-DAC} 1990, Glasgow, Scotland,
UK, March 12-15, 1990},
pages = {589--593},
publisher = {{IEEE} Computer Society},
year = {1990},
url = {https://doi.org/10.1109/EDAC.1990.136715},
doi = {10.1109/EDAC.1990.136715},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/WuZG90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WuG90,
author = {Allen C.{-}H. Wu and
Daniel Gajski},
title = {Partitioning Algorithms for Layout Synthesis from Register-Transfer
Netlists},
booktitle = {{IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD}
1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical
Papers},
pages = {144--147},
publisher = {{IEEE} Computer Society},
year = {1990},
url = {https://doi.org/10.1109/ICCAD.1990.129864},
doi = {10.1109/ICCAD.1990.129864},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/WuG90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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