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ORCIDGerrit den Besten
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- affiliation: NXP Semiconductors, Eindhoven, The Netherlands
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2010 – 2019
- 2019
[c10]Gerrit W. den Besten:
Single-Pair Automotive PHY Solutions from 10Mb/s to 10Gb/s and Beyond. ISSCC 2019: 474-476- 2016
- [c9]Ichiro Fujimori, Martin Brox, Elad Alon, Pavan Kumar Hanumolu, Gerrit den Besten, Hideyuki Nosaka:
F4: Emerging short-reach and high-density interconnect solutions for internet of everything. ISSCC 2016: 502-505 - 2015
- [c8]Gerrit den Besten, Ajith Amerasekera:
Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee. ISSCC 2015: 174-175 - 2013
- [c7]Gerrit den Besten, Harold G. Hanson, Ranjeet K. Gupta:
Current-steering pre-emphasis transmitter with continuously tuned line terminations for optimum impedance match and maximum signal drive range. CICC 2013: 1-4 - [c6]Gerrit den Besten, Koichi Yamaguchi:
Session 23 overview: Short-reach links, XCVR techniques, & PLLs. ISSCC 2013: 398-399 - [c5]Elad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi:
F3: Emerging technologies for wireline communication. ISSCC 2013: 504-505 - 2012
- [j4]Arnoud P. van der Wel, Gerrit den Besten:
A 1.2-6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 µm CMOS. IEEE J. Solid State Circuits 47(7): 1768-1775 (2012) - [c4]Gerrit den Besten, Shunichi Kaeriyama:
High-speed wireline transceivers and clocking. CICC 2012: 1-2 - 2011
- [c3]Arnoud P. van der Wel, Gerrit den Besten:
A 1.2-6 Gb/s, 4.2 pJ/bit Clock & Data Recovery circuit with high jitter tolerance in 0.14μm CMOS. ESSCIRC 2011: 167-170
2000 – 2009
- 2009
- [j3]William Redman-White, Martin Bugbee, Steve Dobbs, Xinyan Wu, Richard A. H. Balmford, Jonah Nuttgens, Umer Salim Kiani, Richard Clegg, Gerrit W. den Besten:
A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock and Data Recovery. IEEE J. Solid State Circuits 44(7): 1914-1926 (2009) - 2008
- [j2]Friedel Gerfers, Gerrit W. den Besten, Pavel V. Petkov, Jim E. Conder, Andreas J. Koellmann:
A 0.2-2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer. IEEE J. Solid State Circuits 43(6): 1436-1448 (2008) - [c2]William Redman-White, Martin Bugbee, Steve Dobbs, Xinyan Wu, Richard A. H. Balmford, Jonah Nuttgens, Umer Salim Kiani, Richard Clegg, Gerrit W. den Besten:
A robust 1.5Gb/s + 3Gb/s serial PHY with feed-forward correction clock and data recovery. ESSCIRC 2008: 170-173 - 2000
- [c1]Joep L. W. Kessels, Gerrit den Besten, Ad M. G. Peeters, Torsten Kramer, Volker Timm:
Applying Asynchronous Circuits in Contactless Smart Cards. ASYNC 2000: 36-44
1990 – 1999
- 1998
- [j1]Gerrit W. den Besten, Bram Nauta
:
Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology. IEEE J. Solid State Circuits 33(7): 956-962 (1998)
Coauthor Index
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