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Chee-Kian Ong
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2000 – 2009
- 2008
- [j3]Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang:
A Clock-Less Jitter Spectral Analysis Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(8): 2263-2272 (2008) - 2006
- [j2]Dongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng:
Bit-Error-Rate Estimation for High-Speed Serial Links. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2616-2627 (2006) - 2004
- [j1]Chee-Kian Ong, Kwang-Ting Cheng, Li-C. Wang:
A new sigma-delta modulator architecture for testing using digital stimulus. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(1): 206-213 (2004) - [c9]Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang:
Jitter spectral extraction for multi-gigahertz signal. ASP-DAC 2004: 298-303 - [c8]Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang:
Random Jitter Extraction Technique in a Multi-Gigahertz Signal. DATE 2004: 286-291 - [c7]Dongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng:
BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics. ITC 2004: 1138-1147 - [c6]Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang:
A Scalable On-Chip Jitter Extraction Technique. VTS 2004: 267-272 - 2003
- [c5]Chee-Kian Ong, Kwang-Ting (Tim) Cheng, Li-C. Wang:
Delta-sigma modulator based mixed-signal BIST architecture for SoC. ASP-DAC 2003: 669-674 - 2002
- [c4]Chee-Kian Ong, Kwang-Ting (Tim) Cheng:
Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus. VTS 2002: 123-128 - 2000
- [c3]Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu:
An FPGA-based re-configurable functional tester for memory chips. Asian Test Symposium 2000: 51-57 - [c2]Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng:
A BIST Scheme for On-Chip ADC and DAC Testing. DATE 2000: 216-220 - [c1]Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng:
Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. VTS 2000: 237-246
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