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Daniel L. Stasiak

D. L. Stasiak

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2000 – 2009

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2006
[j4]
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  - journals/jssc/PhamABBCCHHJKKK06
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Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa:
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. IEEE J. Solid State Circuits 41(1): 179-196 (2006)
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Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong:
A cycle accurate power estimation tool. ASP-DAC 2006: 867-870
2005
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  - journals/micro/StasiakCCPWWWW05
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Daniel L. Stasiak, Rajat Chaudhry, Dennis Cox, Stephen D. Posluszny, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Michael Wang:
Cell Processor Low-Power Design Methodology. IEEE Micro 25(6): 71-78 (2005)
2001
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Daniel L. Stasiak, Farnaz Mounes-Toussi, Salvatore N. Storino:
A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology. IEEE J. Solid State Circuits 36(10): 1546-1552 (2001)
2000
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David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel:
Custom circuit design as a driver of microprocessor performance. IBM J. Res. Dev. 44(6): 799-822 (2000)

1990 – 1999

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1999
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J. V. Tran, Farnaz Mounes-Toussi, S. N. Storino, D. L. Stasiak:
SOI Implementation of a 64-Bit Adder. ICCD 1999: 573-

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