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H. Ekin Sumbul
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2020 – today
- 2024
- [c10]Tony F. Wu, Huichu Liu, H. Ekin Sumbul, Lita Yang, Dipti Baheti, Jeremy Coriell, William Koven, Anu Krishnan, Mohit Mittal, Matheus Trevisan Moreira, Max Waugaman, Laurent Ye, Edith Beigné:
11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. ISSCC 2024: 210-212 - 2023
- [c9]Matheus Trevisan Moreira, William Koven, Tony F. Wu, H. Ekin Sumbul, Edith Beigné:
A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. ASYNC 2023: 58-59 - 2022
- [c8]H. Ekin Sumbul, Tony F. Wu, Yuecheng Li, Syed Shakib Sarwar, William Koven, Eli Murphy-Trotzky, Xingxing Cai, Elnaz Ansari, Daniel H. Morris, Huichu Liu, Doyun Kim, Edith Beigné:
System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars. CICC 2022: 1-8 - [c7]Linyan Mei, Huichu Liu, Tony F. Wu, H. Ekin Sumbul, Marian Verhelst, Edith Beigné:
A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows. DATE 2022: 220-225 - [c6]Daniel H. Morris, Huichu Liu, Tony F. Wu, H. Ekin Sumbul, Elnaz Ansari, Alexandre Barachant, Jonathan Reid, Edith Beigné:
Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications. VLSI Technology and Circuits 2022: 216-217 - [i2]Dominika Przewlocka-Rus, Syed Shakib Sarwar, H. Ekin Sumbul, Yuecheng Li, Barbara De Salvo:
Power-of-Two Quantization for Low Bitwidth and Hardware Compliant Neural Networks. CoRR abs/2203.05025 (2022) - [i1]Zhongnan Qu, Syed Shakib Sarwar, Xin Dong, Yuecheng Li, H. Ekin Sumbul, Barbara De Salvo:
DRESS: Dynamic REal-time Sparse Subnets. CoRR abs/2207.00670 (2022)
2010 – 2019
- 2015
- [c5]H. Ekin Sumbul, Kaushik Vaidyanathan, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi:
A synthesis methodology for application-specific logic-in-memory designs. DAC 2015: 196:1-196:6 - 2014
- [c4]Kaushik Vaidyanathan, Bishnu Prasad Das, H. Ekin Sumbul, Renzhi Liu, Larry T. Pileggi:
Building trusted ICs using split fabrication. HOST 2014: 1-6 - [c3]Kaushik Vaidyanathan, Renzhi Liu, H. Ekin Sumbul, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi:
Efficient and secure intellectual property (IP) design with split fabrication. HOST 2014: 13-18 - 2013
- [c2]Qiuling Zhu, Berkin Akin, H. Ekin Sumbul, Fazle Sadi, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing. 3DIC 2013: 1-7 - [c1]Qiuling Zhu, Tobias Graf, H. Ekin Sumbul, Larry T. Pileggi, Franz Franchetti:
Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware. HPEC 2013: 1-6
Coauthor Index
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last updated on 2024-03-21 02:43 CET by the dblp team
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