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Chris R. Jesshope
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Publications
- 2014
- [j34]Muhammad Irfan Uddin, Raphael Poss, Chris R. Jesshope:
Cache-based high-level simulation of microthreaded many-core architectures. J. Syst. Archit. 60(7): 529-552 (2014) - [j33]Qiang Yang, Jian Fu, Raphael Poss, Chris R. Jesshope:
On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches. ACM Trans. Embed. Comput. Syst. 13(3s): 103:1-103:21 (2014) - [c56]Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
Rethread: A Low-Cost Transient Fault Recovery Scheme for Multithreaded Processors. ARES 2014: 88-93 - [c55]Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
A fault detection mechanism in a Data-flow scheduled Multithreaded processor. DATE 2014: 1-4 - [c54]Muhammad Irfan Uddin, Raphael Poss, Chris R. Jesshope:
Analytical-Based High-Level Simulation of the Microthreaded Many-Core Architectures. PDP 2014: 344-351 - [c53]Muhammad Irfan Uddin, Raphael Poss, Chris R. Jesshope:
Signature-based high-level simulation of microthreaded many-core architectures. SIMULTECH 2014: 509-516 - 2013
- [j32]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Muhammad Irfan Uddin, Chris R. Jesshope:
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management. Microprocess. Microsystems 37(8-C): 1090-1101 (2013) - [c52]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Muhammad Irfan Uddin, Chris R. Jesshope:
MGSim - A simulation environment for multi-core research and education. ICSAMOS 2013: 80-87 - [c51]Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
On-demand thread-level fault detection in a concurrent programming environment. ICSAMOS 2013: 255-262 - [i1]Mike Lankamp, Raphael 'kena' Poss, Qiang Yang, Jian Fu, Muhammad Irfan Uddin, Chris R. Jesshope:
MGSim - Simulation tools for multi-core processor architectures. CoRR abs/1302.1390 (2013) - 2012
- [c50]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Chris R. Jesshope:
Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management. DSD 2012: 501-508 - [c49]Muhammad Irfan Uddin, Chris R. Jesshope, Michiel W. van Tol, Raphael Poss:
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores. RAPIDO 2012: 1-8 - 2011
- [j31]Muhammad Irfan Uddin, Michiel W. van Tol, Chris R. Jesshope:
High Level Simulation of SVP Many-Core Systems. Parallel Process. Lett. 21(4): 413-438 (2011) - [c48]Qiang Yang, Chris R. Jesshope, Jian Fu:
A Micro Threading Based Concurrency Model for Parallel Computing. IPDPS Workshops 2011: 1668-1674 - [c47]Michiel W. van Tol, Roy Bakker, Merijn Verstraaten, Clemens Grelck, Chris R. Jesshope:
Efficient Memory Copy Operations on the 48-core Intel SCC Processor. MARC Symposium 2011: 13-18 - [c46]Merijn Verstraaten, Clemens Grelck, Michiel W. van Tol, Roy Bakker, Chris R. Jesshope:
Mapping Distributed S-Net on the 48-core Intel SCC processor. MARC Symposium 2011: 41-46 - [c45]Clemens Grelck, Kevin Hammond, Heinz Hertlein, Philip K. F. Hölzenspies, Chris R. Jesshope, Raimund Kirner, Bernd Scheuermann, Alexander V. Shafarenko, Iraneus te Boekhorst, Volkmar Wieser:
Engineering Concurrent Software Guided by Statistical Performance Analysis. PARCO 2011: 385-394 - 2010
- [j30]Thomas A. M. Bernard, Clemens Grelck, Chris R. Jesshope:
On the Compilation of a Language for General Concurrent Target Architectures. Parallel Process. Lett. 20(1): 51-69 (2010) - [c44]Thomas A. M. Bernard, Clemens Grelck, Michael A. Hicks, Chris R. Jesshope, Raphael Poss:
Resource-Agnostic Programming for Many-Core Microgrids. Euro-Par Workshops 2010: 109-116 - [c43]Michiel W. van Tol, Chris R. Jesshope:
An Operating System Strategy for General-purpose Parallel Computing on Many-core Architectures. High Performance Computing Workshop 2010: 157-181 - [c42]Michael A. Hicks, Michiel W. van Tol, Chris R. Jesshope:
Towards scalable I/O on a many-core architecture. ICSAMOS 2010: 341-348 - 2009
- [j29]Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp:
Implementation and evaluation of a microthread architecture. J. Syst. Archit. 55(3): 149-161 (2009) - [j28]Michiel W. van Tol, Chris R. Jesshope, Mike Lankamp, Simon Polstra:
An implementation of the SANE Virtual Processor using POSIX threads. J. Syst. Archit. 55(3): 162-169 (2009) - [j27]Chris R. Jesshope, Mike Lankamp, Li Zhang:
The implementation of an SVP many-core processor and the evaluation of its memory architecture. SIGARCH Comput. Archit. News 37(2): 38-45 (2009) - [c41]Chris R. Jesshope, Mike Lankamp, Li Zhang:
Evaluating CMPs and Their Memory Architecture. ARCS 2009: 246-257 - [c39]Chris R. Jesshope, Michael A. Hicks, Mike Lankamp, Raphael 'kena' Poss, Li Zhang:
Making multi-cores mainstream - from security to scalability. PARCO 2009: 16-31 - 2008
- [c38]Chris R. Jesshope, Alexander V. Shafarenko:
Concurrency engineering. ACSAC 2008: 1-8 - [c37]Thuy Duong Vu, Li Zhang, Chris R. Jesshope:
The Verification of the On-Chip COMA Cache Coherence Protocol. AMAST 2008: 413-429 - [c35]Thomas A. M. Bernard, Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp, Michiel W. van Tol, Li Zhang:
A general model of concurrency and its implementation as many-core dynamic RISC processors. ICSAMOS 2008: 1-9 - [c33]Chris R. Jesshope, Jean-Marc Philippe, Michiel W. van Tol:
An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency. SAMOS 2008: 218-228 - 2007
- [j25]Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope:
Asynchronous arbiter for micro-threaded chip multiprocessors. J. Syst. Archit. 53(5-6): 253-262 (2007) - [c32]Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope:
High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids. AICCSA 2007: 301-308 - [c31]Li Zhang, Chris R. Jesshope:
On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores. Euro-Par Workshops 2007: 38-48 - [c30]Thuy Duong Vu, Chris R. Jesshope:
Formalizing SANE Virtual Processor in Thread Algebra. ICFEM 2007: 345-365 - [c29]Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg:
Strategies for Compiling µ TC to Novel Chip Multiprocessors. SAMOS 2007: 127-138 - 2006
- [j24]Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope:
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors. Comput. J. 49(2): 211-233 (2006) - [j23]Chris R. Jesshope, Alexander V. Shafarenko:
Special issue on Micro-grids - Guest Editor Introduction. Int. J. Parallel Program. 34(3): 189-192 (2006) - [j22]Chris R. Jesshope, Alexander V. Shafarenko:
Guest Editor's Introduction (Part 2). Int. J. Parallel Program. 34(4): 319-322 (2006) - [j21]Ian M. Bell, Nabil Hasasneh, Chris R. Jesshope:
Supporting Microthread Scheduling and Synchronisation in CMPs. Int. J. Parallel Program. 34(4): 343-381 (2006) - [c27]Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope:
Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors. ARCS 2006: 252-267 - 2005
- [c25]Kostas Bousias, Chris R. Jesshope:
The Challenges of Massive On-Chip Concurrency. Asia-Pacific Computer Systems Architecture Conference 2005: 157-170 - 1997
- [j17]Julian A. B. Dines, John F. Snowdon, Marc P. Y. Desmulliez, Dima B. Barsky, Alexander V. Shafarenko, Chris R. Jesshope:
Optical Interconnectivity in a Scalable Data-Parallel System. J. Parallel Distributed Comput. 41(1): 120-130 (1997) - 1996
- [c11]Julian A. B. Dines, John F. Snowdon, Marc P. Y. Desmulliez, D. T. Nielson, Dima B. Barsky, Alexander V. Shafarenko, Chris R. Jesshope:
Optical Interconnection hardware for scalable systems. PDPTA 1996: 367-374
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