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Koichi Yamaguchi
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Publications
- 2013
- [c10]Gerrit den Besten, Koichi Yamaguchi:
Session 23 overview: Short-reach links, XCVR techniques, & PLLs. ISSCC 2013: 398-399 - [c9]Ken'ichiro Hijioka, Masaharu Matsudaira, Koichi Yamaguchi, Masayuki Mizuno:
A 5.5Gb/s 5mm contactless interface containing a 50Mb/s bidirectional sub-channel employing common-mode OOK signaling. ISSCC 2013: 406-407 - 2011
- [j7]Koichi Yamaguchi, Masayuki Mizuno:
Dicode Partial Response Signaling over Inductively-Coupled Channel. IEICE Trans. Electron. 94-C(4): 613-618 (2011) - [j6]Koichi Yamaguchi, Masayuki Mizuno:
A Duobinary Signaling for Asymmetric Multi-Chip Communication. IEICE Trans. Electron. 94-C(4): 619-626 (2011) - 2010
- [j5]Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno:
A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors. IEEE J. Solid State Circuits 45(1): 15-22 (2010) - [c8]Tsutomu Takeya, Kazuhisa Sunaga, Koichi Yamaguchi, Hideyuki Sugita, Yoichi Yoshida, Masayuki Mizuno, Tadahiro Kuroda:
A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications. CICC 2010: 1-4 - [c7]Hideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno:
A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS. ISSCC 2010: 162-163 - 2009
- [j4]Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama:
A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery. IEEE J. Solid State Circuits 44(12): 3560-3567 (2009) - [c5]Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno:
A chip-stacked memory for on-chip SRAM-rich SoCs and processors. ISSCC 2009: 60-61 - [c4]Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama:
A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery. ISSCC 2009: 192-193 - [c3]Kazuhisa Sunaga, Hideyuki Sugita, Koichi Yamaguchi, Kazumasa Suzuki:
An 18Gb/s duobinary receiver with a CDR-assisted DFE. ISSCC 2009: 274-275
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