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ORCIDH. Peter Hofstee
Person information
- affiliation: TU Delft, The Netherlands
- affiliation: IBM Research Austin, TX, USA
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Journal Articles
- 2022
[j31]Christophe Bobda
, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, Miriam Leeser, Martin C. Herbordt, Hafsah Shahzad, H. Peter Hofstee, Burkhard Ringlein, Jakub Szefer, Ahmed Sanaullah, Russell Tessier:
The Future of FPGA Acceleration in Datacenters and the Cloud. ACM Trans. Reconfigurable Technol. Syst. 15(3): 34:1-34:42 (2022)- 2021
- [j30]Bedri Sendir, Madhusudhan Govindaraju, Rei Odaira, H. Peter Hofstee:
Low Latency and High Throughput Write-Ahead Logging Using CAPI-Flash. IEEE Trans. Cloud Comput. 9(3): 1129-1142 (2021) - [j29]Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee:
Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow. J. Signal Process. Syst. 93(5): 565-586 (2021) - 2020
- [j28]Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee:
REAF: Reducing Approximation of Channels by Reducing Feature Reuse Within Convolution. IEEE Access 8: 169957-169965 (2020) - [j27]Tanveer Ahmad, Nauman Ahmed, Zaid Al-Ars, H. Peter Hofstee:
Optimizing performance of GATK workflows using Apache Arrow In-Memory data framework. BMC Genom. 21(S-10) (2020) - [j26]Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee:
Tydi: An Open Specification for Complex Data Structures Over Hardware Streams. IEEE Micro 40(4): 120-130 (2020) - [j25]Jian Fang, Yvo T. B. Mulder, Jan Hidders, Jinho Lee, H. Peter Hofstee:
In-memory database acceleration on FPGAs: a survey. VLDB J. 29(1): 33-59 (2020) - [j24]Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee:
An Efficient High-Throughput LZ77-Based Decompressor in Reconfigurable Logic. J. Signal Process. Syst. 92(9): 931-947 (2020) - 2018
- [j23]Raphael Polig, Kubilay Atasu, Heiner Giefers, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee:
A hardware compilation framework for text analytics queries. J. Parallel Distributed Comput. 111: 260-272 (2018) - 2017
- [j22]Jinho Lee, Heesu Kim, Sungjoo Yoo, Kiyoung Choi, H. Peter Hofstee, Gi-Joon Nam, Mark Nutter, Damir A. Jamsek:
ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator. Proc. VLDB Endow. 10(12): 1706-1717 (2017) - 2016
- [j21]Minghua Li, Guancheng Chen, Qijun Wang, Yonghua Lin, H. Peter Hofstee, Per Stenström, Dian Zhou:
PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor. IEEE Comput. Archit. Lett. 15(1): 37-40 (2016) - 2015
- [j20]Fadi H. Gebara, H. Peter Hofstee, Kevin J. Nowka:
Second-Generation Big Data Systems. Computer 48(1): 36-41 (2015) - [j19]Hua-Yu Chang, Iris Hui-Ru Jiang, H. Peter Hofstee, Damir A. Jamsek, Gi-Joon Nam:
Feature detection for image analytics via FPGA acceleration. IBM J. Res. Dev. 59(2/3) (2015) - 2014
- [j18]Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Huaiyu Zhu, Eva Sitaridi:
Giving Text Analytics a Boost. IEEE Micro 34(4): 6-14 (2014) - 2013
- [j17]H. Peter Hofstee, Guan-Cheng Chen, Fadi H. Gebara, Kevin Hall, Jay Herring, Damir A. Jamsek, Jian Li, Yan Li, Juwei Shi, Peter Wai Yee Wong:
Understanding system design for Big Data workloads. IBM J. Res. Dev. 57(3/4): 3 (2013) - [j16]Anne E. Gattiker, Fadi H. Gebara, H. Peter Hofstee, J. D. Hayes, A. Hylick:
Big Data text-oriented benchmark creation for Hadoop. IBM J. Res. Dev. 57(3/4): 10 (2013) - [j15]John S. Liberty, Adrian Barrera, David W. Boerstler, Thomas B. Chadwick, Scott R. Cottier, H. Peter Hofstee, Julie A. Rosser, Marty L. Tsai:
True hardware random number generation implemented in the 32-nm SOI POWER7+ processor. IBM J. Res. Dev. 57(6) (2013) - 2007
- [j14]H. Peter Hofstee, Ashwini K. Nanda, John J. Ritsko:
Preface. IBM J. Res. Dev. 51(5): 501-502 (2007) - [j13]Kanna Shimizu, H. Peter Hofstee, John S. Liberty:
Cell Broadband Engine processor vault security architecture. IBM J. Res. Dev. 51(5): 521-528 (2007) - [j12]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata:
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. 51(5): 529-544 (2007) - 2006
- [j11]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata:
The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid State Circuits 41(1): 63-70 (2006) - [j10]Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa:
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. IEEE J. Solid State Circuits 41(1): 179-196 (2006) - [j9]Michael Gschwind, H. Peter Hofstee, Brian K. Flachs, Martin Hopkins, Yukio Watanabe, Takeshi Yamazaki:
Synergistic Processing in Cell's Multicore Architecture. IEEE Micro 26(2): 10-24 (2006) - 2005
- [j8]James A. Kahle, Michael N. Day, H. Peter Hofstee, Charles R. Johns, Theodore R. Maeurer, David J. Shippy:
Introduction to the Cell multiprocessor. IBM J. Res. Dev. 49(4-5): 589-604 (2005) - 2001
- [j7]H. Peter Hofstee, Jun Sawada:
Derivation of a rotator circuit with homogeneous interconnect. Inf. Process. Lett. 77(2-4): 131-135 (2001) - [j6]Wendy Belluomini, Chris J. Myers, H. Peter Hofstee:
Timed circuit verification using TEL structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 129-146 (2001) - 2000
- [j5]David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel:
Custom circuit design as a driver of microprocessor performance. IBM J. Res. Dev. 44(6): 799-822 (2000) - 1998
- [j4]Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric:
A 1.0-GHz single-issue 64-bit powerPC integer processor. IEEE J. Solid State Circuits 33(11): 1600-1608 (1998) - [j3]H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi:
Designing for a gigahertz [guTS integer processor]. IEEE Micro 18(3): 66-74 (1998) - 1994
- [j2]H. Peter Hofstee:
Distributing a Class of Sequential Programs. Sci. Comput. Program. 22(1-2): 45-65 (1994) - 1990
- [j1]H. Peter Hofstee, Alain J. Martin, Jan L. A. van de Snepscheut:
Distributed Sorting. Sci. Comput. Program. 15(2-3): 119-133 (1990)
Conference and Workshop Papers
- 2023
- [c47]Casper Cromjongh, Yongding Tian, H. Peter Hofstee, Zaid Al-Ars:
Tydi-Chisel: Collaborative and Interface-Driven Data-Streaming Accelerators. NorCAS 2023: 1-7 - [c46]Yongding Tian, Matthijs A. Reukers, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten:
Tydi-lang: A Language for Typed Streaming Hardware. SC Workshops 2023: 520-529 - [c45]Zaid Al-Ars, Jakoba Petri-Koenig, Joost Hoozemans, Luc Dierick, H. Peter Hofstee:
OctoRay: Framework for Scalable FPGA Cluster Acceleration of Python Big Data Applications. SC Workshops 2023: 539-546 - [c44]Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten:
An Intermediate Representation for Composable Typed Streaming Dataflow Designs. VLDB Workshops 2023 - 2022
- [c43]Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars:
Improving Gradient Paths for Binary Convolutional Neural Networks. BMVC 2022: 281 - [c42]Seongyeon Park, Hajin Kim, Tanveer Ahmad, Nauman Ahmed, Zaid Al-Ars, H. Peter Hofstee, Youngsok Kim, Jinho Lee:
SALoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs. IPDPS 2022: 728-738 - [c41]Tanveer Ahmad, Chengxin Ma, Zaid Al-Ars, H. Peter Hofstee:
Communication-Efficient Cluster Scalable Genomics Data Processing Using Apache Arrow Flight. ISPDC 2022: 138-146 - 2021
- [c40]Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars:
An Attention Module for Convolutional Neural Networks. ICANN (1) 2021: 167-178 - [c39]Baozhou Zhu, H. Peter Hofstee, Johan Peltenburg, Jinho Lee, Zaid Al-Ars:
AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression. IJCAI 2021: 3470-3476 - 2020
- [c38]Johan Peltenburg, Lars T. J. van Leeuwen, Joost Hoozemans, Jian Fang, Zaid Al-Ars, H. Peter Hofstee:
Battling the CPU Bottleneck in Apache Parquet to Arrow Conversion Using FPGA. FPT 2020: 281-286 - [c37]Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee:
NASB: Neural Architecture Search for Binary Convolutional Neural Networks. IJCNN 2020: 1-8 - [c36]Christian Pinto, Dimitris Syrivelis, Michele Gazzetti, Panos K. Koutsovasilis, Andrea Reale, Kostas Katrinis, H. Peter Hofstee:
ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation. MICRO 2020: 868-880 - 2019
- [c35]Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars:
Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow. ARC 2019: 32-47 - [c34]Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee:
Refine and Recycle: A Method to Increase Decompression Parallelism. ASAP 2019: 272-280 - [c33]Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee:
A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model. FCCM 2019: 335 - [c32]Johan Peltenburg, Jeroen van Straten, Lars Wijtemans, Lars van Leeuwen, Zaid Al-Ars, H. Peter Hofstee:
Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow. FPL 2019: 270-277 - [c31]Mayoore Jaiswal, H. Peter Hofstee, Valerie Chen, Suvadip Paul, Rogério Feris, Frank Liu, Anupama Jagannathan, Anne Gattiker, Inseok Hwang, Jinho Lee, Matthew Tong, Sahil Dureja, Soham Shah:
Video-Text Compliance: Activity Verification Based on Natural Language Instructions. ICCV Workshops 2019: 1503-1512 - 2018
- [c30]Bedri Sendir, Madhusudhan Govindaraju, Rei Odaira, H. Peter Hofstee:
CAPI-Flash Accelerated Persistent Read Cache for Apache Cassandra. IEEE CLOUD 2018: 220-228 - [c29]Jian Fang, Jianyu Chen, Zaid Al-Ars, H. Peter Hofstee, Jan Hidders:
A high-bandwidth snappy decompressor in reconfigurable logic: work-in-progress. CODES+ISSS 2018: 16 - [c28]Gordon C. Fossum, Ting Wang, H. Peter Hofstee:
A 64-GB Sort at 28 GB/s on a 4-GPU POWER9 Node for Uniformly-Distributed 16-Byte Records with 8-Byte Keys. ISC Workshops 2018: 373-386 - 2017
- [c27]Hamid Mushtaq, Frank Liu, Carlos Costa, Gang Liu, H. Peter Hofstee, Zaid Al-Ars:
SparkGA: A Spark Framework for Cost Effective, Fast and Accurate DNA Analysis at Scale. BCB 2017: 148-157 - [c26]Jian Fang, Jinho Lee, H. Peter Hofstee, Jan Hidders:
Analyzing In-Memory Hash Join: Granularity Matters. ADMS@VLDB 2017: 18-25 - 2016
- [c25]Bedri Sendir, Madhusudhan Govindaraju, Rei Odaira, H. Peter Hofstee:
Optimized Durable Commitlog for Apache Cassandra Using CAPI-Flash. CLOUD 2016: 156-163 - [c24]Zhen Jia, Chao Xue, Guancheng Chen, Jianfeng Zhan, Lixin Zhang, Yonghua Lin, H. Peter Hofstee:
Auto-tuning Spark Big Data Workloads on POWER8: Prediction-Based Dynamic SMT Threading. PACT 2016: 387-400 - [c23]H. Peter Hofstee, Patrick Lysaght, Dirk van den Heuvel:
RAW 2016 Keynotes. IPDPS Workshops 2016: 103-104 - 2014
- [c22]Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee:
Hardware-accelerated text analytics. Hot Chips Symposium 2014: 1-24 - 2009
- [c21]H. Peter Hofstee:
The Next 25 Years of Computer Architecture? Euro-Par Workshops 2009: 7 - [c20]Martti Forsell, H. Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff:
HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? Euro-Par Workshops 2009: 9-15 - 2008
- [c19]Bernard D. Frischer, Dean Abernathy, Gabriele Guidi, Joel Myers, Cassie Thibodeau, Antonio Salvemini, Pascal Müller, H. Peter Hofstee, Barry Minor:
Rome Reborn. SIGGRAPH New Tech Demos 2008: 34 - 2007
- [c18]Osamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, C. J. Johnson, Stephen D. Posluszny:
Cell Broadband Engine Processor Design Methodology. CICC 2007: 711-716 - [c17]Michael T. Clark, H. Peter Hofstee, Edward J. Barragy, Ian Buck, Stephen W. Keckler:
The future of multi-core technologies. CLUSTER 2007 - 2006
- [c16]Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel:
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. ASP-DAC 2006: 871-878 - [c15]H. Peter Hofstee:
Invited speakers II - Real-time supercomputing and technology for games and entertainment. SC 2006: 199 - 2005
- [c14]Dac C. Pham, Erwin Behnen, Mark Bolliger, H. Peter Hofstee, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Yoshio Masubuchi, Stephen D. Posluszny, Mack W. Riley, Masakazu Suzuoki, Michael Wang, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Kazuaki Yazawa:
The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. CICC 2005: 45-49 - [c13]H. Peter Hofstee, Michael N. Day:
Hardware and software architectures for the CELL processor. CODES+ISSS 2005: 1 - [c12]H. Peter Hofstee:
Power Efficient Processor Architecture and The Cell Processor. HPCA 2005: 258-262 - [c11]H. Peter Hofstee:
Communication and Synchronization in the Cell Processor - Invited Talk. CPA 2005: 397 - 2002
- [c10]H. Peter Hofstee:
Power-Constrained Microprocessor Design. ICCD 2002: 14-16 - 2000
- [c9]Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia:
"Timing closure by design, " a high frequency microprocessor design methodology. DAC 2000: 712-717 - 1999
- [c8]Wendy Belluomini, Chris J. Myers, H. Peter Hofstee:
Verification of Delayed-Reset Domino Circuits Using ATACS. ASYNC 1999: 3-12 - [c7]H. Peter Hofstee, Kevin J. Nowka:
Beyond 1 GHz. CICC 1999: 57-61 - 1998
- [c6]Osamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, Naoaki Aoki:
A 690 ps read-access latency register file for a GHz integer microprocessor. ICCD 1998: 6-10 - [c5]Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo:
Design methodology for a 1.0 GHz microprocessor. ICCD 1998: 17-23 - [c4]David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz:
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. VTS 1998: 234-238 - 1997
- [c3]Kevin J. Nowka, H. Peter Hofstee:
Circuits and Microarchitecture for Gigahertz VLSI Designs. ARVLSI 1997: 284-287 - 1992
- [c2]H. Peter Hofstee:
Distributing a Class of Sequential Programs. MPC 1992: 139-162 - 1991
- [c1]H. Peter Hofstee, Johan J. Lukkien, Jan L. A. van de Snepscheut:
A Distributed Implementation of a Task Pool. Research Directions in High-Level Parallel Programming Languages 1991: 338-348
Parts in Books or Collections
- 2009
- [p1]H. Peter Hofstee:
Heterogeneous Multi-core Processors: The Cell Broadband Engine. Multicore Processors and Systems 2009: 271-295
Editorship
- 2020
- [e2]Eduard Ayguadé, Wen-mei W. Hwu, Rosa M. Badia, H. Peter Hofstee:
ICS '20: 2020 International Conference on Supercomputing, Barcelona Spain, June, 2020. ACM 2020, ISBN 978-1-4503-7983-0 [contents] - 2009
- [e1]Stephen W. Keckler, Kunle Olukotun, H. Peter Hofstee:
Multicore Processors and Systems. Integrated Circuits and Systems, Springer 2009, ISBN 978-1-4419-0262-7 [contents]
Reference Works
- 2011
- [r1]H. Peter Hofstee:
Cell Broadband Engine Processor. Encyclopedia of Parallel Computing 2011: 234-241
Informal and Other Publications
- 2023
- [i11]Seongyeon Park, Hajin Kim, Tanveer Ahmad, Nauman Ahmed, Zaid Al-Ars, H. Peter Hofstee, Youngsok Kim, Jinho Lee:
SaLoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs. CoRR abs/2301.09310 (2023) - [i10]Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten:
An Intermediate Representation for Composable Typed Streaming Dataflow Designs. CoRR abs/2308.13436 (2023) - 2022
- [i9]Tanveer Ahmad, Zaid Al-Ars, H. Peter Hofstee:
Benchmarking Apache Arrow Flight - A wire-speed protocol for data transfer, querying and microservices. CoRR abs/2204.03032 (2022) - [i8]Yongding Tian, Matthijs A. Reukers, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten:
Tydi-lang: A Language for Typed Streaming Hardware. CoRR abs/2212.06259 (2022) - [i7]Yongding Tian, Zaid Al-Ars, H. Peter Hofstee:
Tydi-lang: a language for typed streaming hardware - A manual for future Tydi-lang compiler developers. CoRR abs/2212.11154 (2022) - [i6]Matthijs A. Reukers, H. Peter Hofstee, Zaid Al-Ars:
A Toolchain for Streaming Dataflow Accelerator Designs for Big Data Analytics: Defining an IR for Composable Typed Streaming Dataflow Designs. CoRR abs/2212.12003 (2022) - 2021
- [i5]Baozhou Zhu, H. Peter Hofstee, Johan Peltenburg, Jinho Lee, Zaid Al-Ars:
AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression. CoRR abs/2105.12151 (2021) - [i4]Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars:
An Attention Module for Convolutional Neural Networks. CoRR abs/2108.08205 (2021) - 2020
- [i3]Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee:
NASB: Neural Architecture Search for Binary Convolutional Neural Networks. CoRR abs/2008.03515 (2020) - [i2]Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars:
SoFAr: Shortcut-based Fractal Architectures for Binary Convolutional Neural Networks. CoRR abs/2009.05317 (2020) - 2018
- [i1]Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Eva Sitaridi, Huaiyu Zhu:
Giving Text Analytics a Boost. CoRR abs/1806.01103 (2018)
Coauthor Index
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