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ORCIDEdward J. McCluskey
Edward Joseph McCluskey Jr.
Person information
- affiliation: Stanford University, USA
- award (2012): IEEE John von Neumann Medal
- award (2008): Computer Pioneer Award
- award (1996): IEEE Emanuel R. Piore Award
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Books and Theses
- 1986
[b2]Edward J. McCluskey:
Logic design principles - with emphasis on testable semicustom circuits. Prentice Hall series in computer engineering, Prentice Hall 1986, ISBN 978-0-13-539768-8, pp. I-XIX, 1-549- 1975
- [b1]Hans W. Gschwind, Edward J. McCluskey:
Design of Digital Computers - An Introduction. Texts and Monographs in Computer Science, Springer 1975, ISBN 978-3-642-86192-5, pp. i-ix, 1-548
Journal Articles
- 2016
- [j73]Paolo Montuschi
, Edward J. McCluskey, Samarjit Chakraborty, Jason Cong, Ramón M. Rodríguez-Dagnino, Fred Douglis, Lieven Eeckhout, Gernot Heiser, Sushil Jajodia, Ruby B. Lee, Dinesh Manocha, Tomás F. Pena, Isabelle Puaut, Hanan Samet, Donatella Sciuto:
State of the Journal. IEEE Trans. Computers 65(7): 2014-2018 (2016) - 2010
- [j72]Ahmad A. Al-Yamani, Edward J. McCluskey:
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns. J. Electron. Test. 26(5): 513-521 (2010) - 2005
- [j71]Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey:
Optimized reseeding by seed ordering and encoding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 264-270 (2005) - [j70]Chien-Mo James Li, Edward J. McCluskey:
Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1748-1759 (2005) - [j69]Ahmad A. Al-Yamani, Edward J. McCluskey:
Test chip experimental results on high-level structural test. ACM Trans. Design Autom. Electr. Syst. 10(4): 690-701 (2005) - 2004
- [j68]Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey:
Reconfigurable Architecture for Autonomous Self-Repair. IEEE Des. Test Comput. 21(3): 228-240 (2004) - [j67]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
Efficient Design Diversity Estimation for Combinational Circuits. IEEE Trans. Computers 53(11): 1483-1492 (2004) - 2002
- [j66]Nahmsuk Oh, Subhasish Mitra, Edward J. McCluskey:
ED4I: Error Detection by Diverse Data and Duplicated Instructions. IEEE Trans. Computers 51(2): 180-199 (2002) - [j65]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
A Design Diversity Metric and Analysis of Redundant Systems. IEEE Trans. Computers 51(5): 498-510 (2002) - [j64]Nahmsuk Oh, Philip P. Shirvani, Edward J. McCluskey:
Error detection by duplicated instructions in super-scalar processors. IEEE Trans. Reliab. 51(1): 63-75 (2002) - [j63]Nahmsuk Oh, Philip P. Shirvani, Edward J. McCluskey:
Control-flow checking by software signatures. IEEE Trans. Reliab. 51(1): 111-122 (2002) - [j62]Nahmsuk Oh, Edward J. McCluskey:
Error detection by selective procedure call duplication for low energy consumption. IEEE Trans. Reliab. 51(4): 392-402 (2002) - 2001
- [j61]Nur A. Touba, Edward J. McCluskey:
Bit-fixing in pseudorandom sequences for scan BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4): 545-555 (2001) - 2000
- [j60]Nirmal R. Saxena, Santiago Fernández-Gomez, Wei-Je Huang, Subhasish Mitra, Shu-Yi Yu, Edward J. McCluskey:
Dependable Computing and Online Testing in Adaptive and Configurable Systems. IEEE Des. Test Comput. 17(1): 29-41 (2000) - [j59]Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey:
Efficient Multiplexer Synthesis Techniques. IEEE Des. Test Comput. 17(4): 90-97 (2000) - [j58]Philip P. Shirvani, Nirmal R. Saxena, Edward J. McCluskey:
Software-implemented EDAC protection against SEUs. IEEE Trans. Reliab. 49(3): 273-284 (2000) - [j57]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
Common-mode failures in redundant VLSI systems: a survey. IEEE Trans. Reliab. 49(3): 285-295 (2000) - 1999
- [j56]Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey:
An output encoding problem and a solution technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 761-768 (1999) - [j55]Nur A. Touba, Edward J. McCluskey:
RP-SYN: synthesis of random pattern testable circuits with test point insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8): 1202-1213 (1999) - 1997
- [j54]Nirmal R. Saxena, Edward J. McCluskey:
Parallel Signatur Analysis Design with Bounds on Aliasing. IEEE Trans. Computers 46(4): 425-438 (1997) - [j53]Nur A. Touba, Edward J. McCluskey:
Logic synthesis of multilevel circuits with concurrent error detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 783-789 (1997) - 1996
- [j52]Nirmal R. Saxena, Edward J. McCluskey:
Counting Two-State Transition-Tour Sequences. IEEE Trans. Computers 45(11): 1337-1342 (1996) - 1995
- [j51]Kiyoshi Furuya, Seiji Seki, Edward J. McCluskey:
Design of Autonomous TPG Circuits for Use in Two-Pattern Testing. IEICE Trans. Inf. Syst. 78-D(7): 882-888 (1995) - [j50]Daniel Boley, Gene H. Golub, Samy Makar, Nirmal R. Saxena, Edward J. McCluskey:
Floating Point Fault Tolerance with Backward Error Assertions. IEEE Trans. Computers 44(2): 302-311 (1995) - [j49]Siyad C. Ma, Edward J. McCluskey:
Open faults in BiCMOS gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 567-575 (1995) - 1994
- [j48]Nirmal R. Saxena, Edward J. McCluskey:
Linear Complexity Assertions for Sorting. IEEE Trans. Software Eng. 20(6): 424-431 (1994) - 1993
- [j47]Hong Hao, Edward J. McCluskey:
Analysis of Gate Oxide Shorts in CMOS Circuits. IEEE Trans. Computers 42(12): 1510-1516 (1993) - 1992
- [j46]Nirmal R. Saxena, Piero Franco, Edward J. McCluskey:
Simple Bounds on Serial Signature Analysis Aliasing for Random Testing. IEEE Trans. Computers 41(5): 638-645 (1992) - 1990
- [j45]Edward J. McCluskey:
Design Techniques for Testable Embedded Error Checkers. Computer 23(7): 84-88 (1990) - [j44]Nirmal R. Saxena, Edward J. McCluskey:
Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums. IEEE Trans. Computers 39(4): 554-559 (1990) - [j43]Nirmal R. Saxena, Edward J. McCluskey:
Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks. IEEE Trans. Computers 39(7): 969-975 (1990) - 1988
- [j42]Aamer Mahmood, Edward J. McCluskey:
Concurrent Error Detection Using Watchdog Processors - A Survey. IEEE Trans. Computers 37(2): 160-174 (1988) - [j41]Laung-Terng Wang, Edward J. McCluskey:
Linear Feedback Shift Register Design Using Cyclic Codes. IEEE Trans. Computers 37(10): 1302-1306 (1988) - [j40]Dick L. Liu, Edward J. McCluskey:
Design of large embedded CMOS PLAs for built-in self-test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 50-59 (1988) - [j39]Edward J. McCluskey, Samy Makar, Samiha Mourad, Kenneth D. Wagner:
Probability models for pseudorandom test sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 68-74 (1988) - [j38]Laung-Terng Wang, Edward J. McCluskey:
Hybrid designs generating maximum-length sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 91-99 (1988) - [j37]Laung-Terng Wang, Edward J. McCluskey:
Circuits for pseudoexhaustive test pattern generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10): 1068-1080 (1988) - 1987
- [j36]Dick L. Liu, Edward J. McCluskey:
Designing CMOS Circuits for Switch-Level Testability. IEEE Des. Test 4(4): 42-49 (1987) - [j35]Cary K. Chin, Edward J. McCluskey:
Test Length for Pseudorandom Testing. IEEE Trans. Computers 36(2): 252-256 (1987) - [j34]Kenneth D. Wagner, Cary K. Chin, Edward J. McCluskey:
Pseudorandom Testing. IEEE Trans. Computers 36(3): 332-343 (1987) - 1986
- [j33]Laung-Terng Wang, Edward J. McCluskey:
Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique. IEEE Trans. Computers 35(4): 367-370 (1986) - [j32]Saied Bozorgui-Nesbat, Edward J. McCluskey:
Lower Overhead Design for Testability of Programmable Logic Arrays. IEEE Trans. Computers 35(4): 379-383 (1986) - 1985
- [j31]Edward J. McCluskey:
Built-In Self-Test Techniques. IEEE Des. Test 2(2): 21-28 (1985) - [j30]Edward J. McCluskey:
Built-In Self-Test Structures. IEEE Des. Test 2(2): 29-36 (1985) - 1984
- [j29]Edward J. McCluskey:
Verification Testing - A Pseudoexhaustive Test Technique. IEEE Trans. Computers 33(6): 541-546 (1984) - [j28]Joseph L. A. Hughes, Edward J. McCluskey, David J. Lu:
Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs. IEEE Trans. Computers 33(6): 546-550 (1984) - [j27]Javad Khakbaz, Edward J. McCluskey:
Self-Testing Embedded Parity Checkers. IEEE Trans. Computers 33(8): 753-756 (1984) - [j26]David J. Lu, Edward J. McCluskey:
Quantitative Evaluation of Self-Checking Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(2): 150-155 (1984) - 1982
- [j25]Ravishankar K. Iyer, Steven E. Butner, Edward J. McCluskey:
A Statistical Failure/Load Relationship: Results of a Multicomputer Study. IEEE Trans. Computers 31(7): 697-706 (1982) - 1981
- [j24]Edward J. McCluskey, Saied Bozorgui-Nesbat:
Design for Autonomous Test. IEEE Trans. Computers 30(11): 866-875 (1981) - 1980
- [j23]John P. Hayes, Edward J. McCluskey:
Testability Considerotions in Microprocessor-Based Design. Computer 13(3): 17-26 (1980) - 1979
- [j22]Edward J. McCluskey:
Logic Design of Multivalued I2L Logic Circuits. IEEE Trans. Computers 28(8): 546-559 (1979) - 1978
- [j21]Edward J. McCluskey, Kenneth P. Parker, John J. Shedletsky:
Boolean Network Probabilities and Network Design. IEEE Trans. Computers 27(2): 187-189 (1978) - [j20]Kenneth P. Parker, Edward J. McCluskey:
Sequential Circuit Output Probabilities From Regular Expressions. IEEE Trans. Computers 27(3): 222-231 (1978) - 1977
- [j19]John F. Wakerly, Edward J. McCluskey:
Microcomputers in the Computer Engineering Curriculum. Computer 10(1): 32-38 (1977) - [j18]Tich T. Dao, Edward J. McCluskey, Lewis K. Russel:
Multivalued Integrated Injection Logic. IEEE Trans. Computers 26(12): 1233-1241 (1977) - 1975
- [j17]Kenneth P. Parker, Edward J. McCluskey:
Analysis of Logic Circuits with Faults Using Input Signal Probabilities. IEEE Trans. Computers 24(5): 573-578 (1975) - [j16]Kenneth P. Parker, Edward J. McCluskey:
Probabilistic Treatment of General Combinational Networks. IEEE Trans. Computers 24(6): 668-670 (1975) - 1973
- [j15]Taylor L. Booth, C. Gordon Bell, Cecil H. Coker, Robert M. Glorioso, Edward J. McCluskey, Frederic J. Mowle, David M. Robinson:
Minicomputers in the Digital Laboratory Program. Computer 6(1): 28-42 (1973) - [j14]Martha E. Sloan, Clarence L. Coates, Edward J. McCluskey:
Cosine survey of electrical engineering departments. Computer 6(6): 30-39 (1973) - [j13]Daniel P. Siewiorek, Edward J. McCluskey:
Switch Complexity in Systems with Hybrid Redundancy. IEEE Trans. Computers 22(3): 276-282 (1973) - [j12]Daniel P. Siewiorek, Edward J. McCluskey:
An Iterative Cell Switch Design for Hybrid Redundancy. IEEE Trans. Computers 22(3): 290-297 (1973) - 1971
- [j11]Edward J. McCluskey:
Test and Diagnosis Procedure for Digital Networks. Computer 4(1): 17-20 (1971) - [j10]Edward J. McCluskey, Frederick W. Clegg:
Fault Equivalence in Combinational Logic Networks. IEEE Trans. Computers 20(11): 1286-1293 (1971) - 1968
- [j9]William F. Atchison, Samuel D. Conte, John W. Hamblen, Thomas E. Hull, Thomas A. Keenan, William B. Kehl, Edward J. McCluskey, Silvio O. Navarro, Werner C. Rheinboldt, Earl J. Schweppe, William Viavant, David M. Young:
Curriculum 68: Recommendations for academic programs in computer science: a report of the ACM curriculum committee on computer science. Commun. ACM 11(3): 151-197 (1968) - 1964
- [j8]Janusz A. Brzozowski, Edward J. McCluskey:
About Signal Flow Graph Techniques for Sequential Circuits. IEEE Trans. Electron. Comput. 13(2): 154 (1964) - [j7]Ted A. Dolotta, Edward J. McCluskey:
The Coding of Internal States of Sequential Circuits. IEEE Trans. Electron. Comput. 13(5): 549-562 (1964) - 1963
- [j6]Edward J. McCluskey:
Reduction of Feedback Loops in Sequential Circuits and Carry Leads in Iterative Networks. Inf. Control. 6(2): 99-118 (1963) - [j5]Janusz A. Brzozowski, Edward J. McCluskey:
Signal Flow Graph Techniques for Sequential Circuit State Diagrams. IEEE Trans. Electron. Comput. 12(2): 67-76 (1963) - 1962
- [j4]Insley B. Pyne, Edward Joseph McCluskey Jr.:
The Reduction of Redundancy in Solving Prime Implicant Tables. IRE Trans. Electron. Comput. 11(4): 473-482 (1962) - 1959
- [j3]Edward Joseph McCluskey Jr., Stephen H. Unger:
A Note on the Number of Internal Variable Assignments for Sequential Switching Circuits. IRE Trans. Electron. Comput. 8(4): 439-440 (1959) - 1958
- [j2]Edward J. McCluskey:
Iterative Combinational Switching Networksߞ General Design Considerations. IRE Trans. Electron. Comput. 7(4): 285-291 (1958) - 1957
- [j1]Edward J. McCluskey:
Comments on Determination of Redundancies in a Set of Patterns. IRE Trans. Inf. Theory 3(2): 167 (1957)
Conference and Workshop Papers
- 2008
- [c142]Jaekwang Lee, Edward J. McCluskey:
Failing Frequency Signature Analysis. ITC 2008: 1-8 - [c141]Intaik Park, Edward J. McCluskey:
Launch-on-Shift-Capture Transition Tests. ITC 2008: 1-9 - [c140]François-Fabien Ferhani, Nirmal R. Saxena, Edward J. McCluskey, Phil Nigh:
How Many Test Patterns are Useless? VTS 2008: 23-28 - [c139]Intaik Park, Donghwi Lee, Erik Chmelar, Edward J. McCluskey:
Inconsistent Fail due to Limited Tester Timing Accuracy. VTS 2008: 47-52 - [c138]Jaekwang Lee, Intaik Park, Edward J. McCluskey:
Error Sequence Analysis. VTS 2008: 255-260 - 2007
- [c137]Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey:
California scan architecture for high quality and low power testing. ITC 2007: 1-10 - [c136]Kyoung Youn Cho, Edward J. McCluskey:
Test Set Reordering Using the Gate Exhaustive Test Metric. VTS 2007: 199-204 - 2006
- [c135]François-Fabien Ferhani, Edward J. McCluskey:
Classifying Bad Chips and Ordering Test Sets. ITC 2006: 1-10 - [c134]Erik Chmelar, Edward J. McCluskey:
Session Abstract. VTS 2006: 156-157 - 2005
- [c133]Ahmad A. Al-Yamani, Edward J. McCluskey:
BIST-Guided ATPG. ISQED 2005: 244-249 - [c132]Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey:
Gate exhaustive testing. ITC 2005: 7 - [c131]Intaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey:
Effective TARO Pattern Generation. VTS 2005: 161-166 - 2004
- [c130]Ahmad A. Al-Yamani, Edward J. McCluskey:
Test quality for high level structural test. HLDVT 2004: 109-114 - [c129]Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra:
Speed Clustering of Integrated Circuits. ITC 2004: 1128-1137 - [c128]Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra:
ELF-Murphy Data on Defects and Test Sets. VTS 2004: 16-22 - [c127]Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger:
Delay Defect Screening using Process Monitor Structures. VTS 2004: 43-52 - [c126]Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure:
A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. VTS 2004: 154-170 - 2003
- [c125]Ahmad A. Al-Yamani, Edward J. McCluskey:
Seed encoding with LFSRs and cellular automata. DAC 2003: 560-565 - [c124]Ahmad A. Al-Yamani, Edward J. McCluskey:
Built-In Reseeding for Serial Bist. VTS 2003: 63-68 - [c123]Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey:
Bist Reseeding with very few Seeds. VTS 2003: 69-76 - 2002
- [c122]Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey:
Testing Digital Circuits with Constraints. DFT 2002: 195-206 - [c121]Subhasish Mitra, Edward J. McCluskey:
Dependable Reconfigurable Computing Design Diversity and Self Repair. Evolvable Hardware 2002: 5 - [c120]Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey:
Fault Grading FPGA Interconnect Test Configurations. ITC 2002: 608-617 - [c119]Chao-Wen Tseng, James Li, Edward J. McCluskey:
Experimental Results for Slow-Speed Testing. VTS 2002: 37-42 - [c118]Chien-Mo James Li, Edward J. McCluskey:
Diagnosis of Sequence-Dependent Chips. VTS 2002: 187-192 - [c117]Subhasish Mitra, Edward J. McCluskey, Samy Makar:
Design for Testability and Testing of IEEE 1149.1 Tap Controller. VTS 2002: 247-252 - [c116]Edward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers:
Debating the Future of Burn-In. VTS 2002: 311-314 - 2001
- [c115]Shu-Yi Yu, Edward J. McCluskey:
Permanent Fault Repair for FPGAs with Limited Redundant Area. DFT 2001: 125-133 - [c114]Nahmsuk Oh, Edward J. McCluskey:
Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection Latency. DFT 2001: 182- - [c113]Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey:
Fast Run-Time Fault Location in Dependable FPGA-Based Applications. DFT 2001: 206-214 - [c112]Ahmad A. Al-Yamani, Nahmsuk Oh, Edward J. McCluskey:
Performance Evaluation of Checksum-Based ABFT. DFT 2001: 461- - [c111]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
Techniques for Estimation of Design Diversity for Combinational Logic Circuits. DSN 2001: 25-36 - [c110]Wei-Je Huang, Edward J. McCluskey:
Column-Based Precompiled Configuration Techniques for FPGA. FCCM 2001: 137-146 - [c109]Wei-Je Huang, Edward J. McCluskey:
A memory coherence technique for online transient error recovery of FPGA configurations. FPGA 2001: 183-192 - [c108]Subhasish Mitra, Edward J. McCluskey:
Diversity Techniques for Concurrent Error Detection. ISQED 2001: 249-250 - [c107]Shu-Yi Yu, Edward J. McCluskey:
On-line testing and recovery in TMR systems for real-time applications. ITC 2001: 240-249 - [c106]Chao-Wen Tseng, Edward J. McCluskey:
Multiple-output propagation transition fault test. ITC 2001: 358-366 - [c105]Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey:
Testing for resistive opens and stuck opens. ITC 2001: 1049-1058 - [c104]Chien-Mo James Li, Edward J. McCluskey:
Diagnosis of Tunneling Opens. VTS 2001: 22-27 - [c103]Subhasish Mitra, Edward J. McCluskey:
Design Diversity for Concurrent Error Detection in Sequential Logic Circuts. VTS 2001: 178-183 - [c102]Subhasish Mitra, Edward J. McCluskey:
Design of Redundant Systems Protected Against Common-Mode Failures. VTS 2001: 190-197 - [c101]Chao-Wen Tseng, Ray Chen, Edward J. McCluskey, Phil Nigh:
MINVDD Testing for Weak CMOS ICs. VTS 2001: 339-345 - [c100]Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson:
An Evaluation of Pseudo Random Testing for Detecting Real Defects. VTS 2001: 404-410 - 2000
- [c99]Shu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey:
An ACS Robotic Control Algorithm with Fault Tolerant Capabilities. FCCM 2000: 175-184 - [c98]Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey:
A Reliable LZ Data Compressor on Reconfigurable Coprocessors. FCCM 2000: 249-258 - [c97]Chien-Mo James Li, Edward J. McCluskey:
Testing for tunneling opens. ITC 2000: 85-94 - [c96]Subhasish Mitra, Edward J. McCluskey:
Combinational logic synthesis for diversity in duplex systems. ITC 2000: 179-188 - [c95]Edward J. McCluskey, Chao-Wen Tseng:
Stuck-fault tests vs. actual defects. ITC 2000: 336-343 - [c94]Subhasish Mitra, Edward J. McCluskey:
Which concurrent error detection scheme to choose ? ITC 2000: 985-994 - [c93]Wei-Je Huang, Edward J. McCluskey:
Transient errors and rollback recovery in LZ compression. PRDC 2000: 128-138 - [c92]Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu:
Cold Delay Defect Screening. VTS 2000: 183-188 - [c91]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
Fault Escapes in Duplex Systems. VTS 2000: 453-458 - [c90]Subhasish Mitra, Edward J. McCluskey:
Word Voter: A New Voter Design for Triple Modular Redundant Systems. VTS 2000: 465-470 - 1999
- [c89]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
A design diversity metric and reliability analysis for redundant systems. ITC 1999: 662-671 - [c88]Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey:
Finite state machine synthesis with concurrent error detection. ITC 1999: 672-679 - [c87]Philip P. Shirvani, Edward J. McCluskey:
PADded Cache: A New Fault-Tolerance Technique for Cache Memories. VTS 1999: 440-445 - 1998
- [c86]Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey:
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip. ITC 1998: 184-193 - [c85]Jonathan T.-Y. Chang, Edward J. McCluskey:
Detecting resistive shorts for CMOS domino circuits. ITC 1998: 890-899 - [c84]Nirmal R. Saxena, Edward J. McCluskey:
Dependable adaptive computing systems-the ROAR project. SMC 1998: 2172-2177 - [c83]Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu, Sanjay Wattal, Mike Purtell, Edward J. McCluskey:
Experimental Results for IDDQ and VLV Testing. VTS 1998: 118-125 - 1997
- [c82]Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey:
An output encoding problem and a solution technique. ICCAD 1997: 304-307 - [c81]Nur A. Touba, Edward J. McCluskey:
Pseudo-Random Pattern Testing of Bridging Faults. ICCD 1997: 54-60 - [c80]Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey:
Scan Synthesis for One-Hot Signals. ITC 1997: 714-722 - [c79]Samy Makar, Edward J. McCluskey:
ATPG for scan chain latches and flip-flops. VTS 1997: 364-369 - [c78]Robert B. Norwood, Edward J. McCluskey:
High-Level Synthesis for Orthogonal Sca. VTS 1997: 370-375 - [c77]Jonathan T.-Y. Chang, Edward J. McCluskey:
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs. VTS 1997: 446- - 1996
- [c76]Nur A. Touba, Edward J. McCluskey:
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. ITC 1996: 167-175 - [c75]Jonathan T.-Y. Chang, Edward J. McCluskey:
Detecting Delay Flaws by Very-Low-Voltage Testing. ITC 1996: 367-376 - [c74]Robert B. Norwood, Edward J. McCluskey:
Orthogonal Scan: Low-Overhead Scan for Data Paths. ITC 1996: 659-668 - [c73]Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell:
Analysis and Detection of Timing Failures in an Experimental Test Chip. ITC 1996: 691-700 - [c72]Nur A. Touba, Edward J. McCluskey:
Test point insertion based on path tracing. VTS 1996: 2-8 - [c71]Robert B. Norwood, Edward J. McCluskey:
Synthesis-for-scan and scan chain ordering. VTS 1996: 87-92 - [c70]Jonathan T.-Y. Chang, Edward J. McCluskey:
Quantitative analysis of very-low-voltage testing. VTS 1996: 332-337 - [c69]Nur A. Touba, Edward J. McCluskey:
Applying two-pattern tests using scan-mapping. VTS 1996: 393-399 - 1995
- [c68]Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey:
A simple technique for locating gate-level faults in combinational circuits. Asian Test Symposium 1995: 65-70 - [c67]Samy Makar, Edward J. McCluskey:
Functional Tests for Scan Chain Latches. ITC 1995: 606-615 - [c66]Piero Franco, William D. Farwell, Robert L. Stokes, Edward J. McCluskey:
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design. ITC 1995: 653-662 - [c65]Siyad C. Ma, Piero Franco, Edward J. McCluskey:
An Experimental Chip to Evaluate Test Techniques: Experiment Results. ITC 1995: 663-672 - [c64]Nur A. Touba, Edward J. McCluskey:
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST. ITC 1995: 674-682 - [c63]Shridhar K. Mukund, Edward J. McCluskey, T. R. N. Rao:
An apparatus for pseudo-deterministic testing. VTS 1995: 125-131 - [c62]Samy Makar, Edward J. McCluskey:
Checking experiments to test latches. VTS 1995: 196-201 - [c61]Nur A. Touba, Edward J. McCluskey:
Transformed pseudo-random patterns for BIST. VTS 1995: 410-416 - 1994
- [c60]Nur A. Touba, Edward J. McCluskey:
Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. ICCAD 1994: 651-654 - [c59]Nur A. Touba, Edward J. McCluskey:
Automated Logic Synthesis of Random-Pattern-Testable Circuits. ITC 1994: 174-183 - [c58]Piero Franco, Edward J. McCluskey:
On-line delay testing of digital circuits. VTS 1994: 167-173 - [c57]Siyad C. Ma, Edward J. McCluskey:
Open faults in BiCMOS gates. VTS 1994: 434-439 - [c56]Piero Franco, Edward J. McCluskey:
Three-pattern tests for delay faults. VTS 1994: 452-456 - 1993
- [c55]Hong Hao, Edward J. McCluskey:
Very-Low-Voltage Testing for Weak CMOS Logic ICs. ITC 1993: 275-284 - [c54]Edward J. McCluskey:
Quality and Single-Stuck Faults. ITC 1993: 597 - [c53]LaNae J. Avra, Edward J. McCluskey:
Synthesizing for Scan Dependence in Built-In Self-Testable Desings. ITC 1993: 734-743 - 1992
- [c52]Siyad C. Ma, Edward J. McCluskey:
Non-Conventional Faults in BiCMOS Digital Circuits. ITC 1992: 882-891 - 1991
- [c51]Nirmal R. Saxena, Piero Franco, Edward J. McCluskey:
Bounds on Signature Analysis Aliasing for Random Testing. FTCS 1991: 104-113 - [c50]Steven D. Millman, Edward J. McCluskey:
Bridging, Transition, and Stuck-Open Faults in Self-Testing CMOS Checkers. FTCS 1991: 154-161 - [c49]Hong Hao, Edward J. McCluskey:
"Resistive Shorts" Within CMOS Gates. ITC 1991: 292-301 - [c48]Kiyoshi Furuya, Edward J. McCluskey:
Two-Pattern Test Capabilities of Autonomous TPG Circuits. ITC 1991: 704-711 - [c47]Piero Franco, Edward J. McCluskey:
Delay Testing of Digital Circuits by Output Waveform Analysis. ITC 1991: 798-807 - [c46]Nirmal R. Saxena, Piero Franco, Edward J. McCluskey:
Refined Bounds on Signature Analysis Aliasing for Random Testing. ITC 1991: 818-827 - 1990
- [c45]LaNae J. Avra, Edward J. McCluskey:
Behavioral synthesis of testable systems with VHDL. Compcon 1990: 410-415 - [c44]Steven D. Millman, Edward J. McCluskey, John M. Acken:
Diagnosing CMOS bridging faults with stuck-at fault dictionaries. ITC 1990: 860-870 - 1989
- [c43]Jon G. Jr. Udell, Edward J. McCluskey:
Pseudo-exhaustive test and segmentation: formal definitions and extended fault coverage results. FTCS 1989: 292-298 - [c42]Nirmal R. Saxena, Edward J. McCluskey:
Control-flow checking using watchdog assists and extended-precision checksums. FTCS 1989: 428-435 - [c41]Samy Makar, Edward J. McCluskey:
The critical path for multiple faults. ICCAD 1989: 162-165 - [c40]Nirmal R. Saxena, Edward J. McCluskey:
Arithmetic and galois checksums. ICCAD 1989: 570-573 - 1988
- [c39]Takashi Nanya, Samiha Mourad, Edward J. McCluskey:
Multiple stuck-at fault testability of self-testing checkers. FTCS 1988: 381-386 - [c38]Edward J. McCluskey:
Practice and Theory. ITC 1988: 203-204 - [c37]Edward J. McCluskey, Fred Buelow:
IC Quality and Test Transparency. ITC 1988: 295-301 - [c36]Samy Makar, Edward J. McCluskey:
On the Testing of Multiplexers. ITC 1988: 669-679 - [c35]Steven D. Millman, Edward J. McCluskey:
Detecting Bridging Faults with Stuck-at Test Sets. ITC 1988: 773-783 - [c34]Samiha Mourad, Edward J. McCluskey:
On Benchmarking Digital Testing Systems. ITC 1988: 997 - [c33]Jon G. Udeli Jr., Edward J. McCluskey:
Partial Hardware Partitioning: A New Pseudo-Exhaustive Test Implementation. ITC 1988: 1000 - 1987
- [c32]Hassanein H. Amer, Edward J. McCluskey:
Modeling the Effect of Chip Failures on Cache Memory Systems. ICDE 1987: 340-346 - 1986
- [c31]Samiha Mourad, Joseph L. A. Hughes, Edward J. McCluskey:
Multiple Fault Detection in Parity Trees. COMPCON 1986: 441-444 - [c30]Samiha Mourad, Joseph L. A. Hughes, Edward J. McCluskey:
Stuck-At Fault Detection in Parity Trees. FJCC 1986: 836-840 - [c29]Laung-Terng Wang, Edward J. McCluskey:
Circuits for Pseudo-Exhaustive Test Pattern Generation. ITC 1986: 25-37 - [c28]Laung-Terng Wang, Edward J. McCluskey:
A Hybrid Design of Maximum-Length Sequence Generators. ITC 1986: 38-47 - [c27]Greg G. Freeman, Dick L. Liu, Bruce A. Wooley, Edward J. McCluskey:
Two CMOS Metastability Sensors. ITC 1986: 140-144 - [c26]Joseph L. A. Hughes, Edward J. McCluskey:
Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets. ITC 1986: 368-374 - [c25]Mario Lúcio Côrtes, Edward J. McCluskey:
An Experiment on Intermittent-Failure Mechanisms. ITC 1986: 435-442 - 1985
- [c24]Edward J. McCluskey:
Hardware Fault-Tolerance. COMPCON 1985: 260-263 - [c23]Joseph L. A. Hughes, Samiha Mourad, Edward J. McCluskey:
An Experimental Study Comparing 74LS181 Test Sets. COMPCON 1985: 384-387 - [c22]Cary K. Chin, Edward J. McCluskey:
Test Length for Pseudo Random Testing. ITC 1985: 94-99 - [c21]Aamer Mahmood, Edward J. McCluskey, Aydin Ersoz:
Concurrent System-Level Error Detection Using a Watchdog Processor. ITC 1985: 145-152 - [c20]Edward J. McCluskey:
Test Teaching. ITC 1985: 235 - 1984
- [c19]Joseph L. A. Hughes, Edward J. McCluskey:
An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets. ITC 1984: 52-58 - [c18]Syed Zahoor Hassan, Edward J. McCluskey:
Pseudo-Exhaustive Testing of Sequential Machines Using Signature Analysis. ITC 1984: 320-326 - [c17]Saied Bozorgui-Nesbat, Edward J. McCluskey:
Lower Overhead Design for Testability of Programmable Logic Arrays. ITC 1984: 856-865 - 1983
- [c16]Edward J. McCluskey, David J. Lu:
Recurrent Test Patterns. ITC 1983: 76-82 - [c15]Edward J. McCluskey:
Teaching Testing. ITC 1983: 166-169 - [c14]Aamer Mahmood, Edward J. McCluskey, David J. Lu:
Concurrent Fault Detection Using a Watchdog Processor and Assertions. ITC 1983: 622-628 - 1982
- [c13]Edward J. McCluskey:
Verification testing. DAC 1982: 495-500 - [c12]Edward J. McCluskey:
Built-In Verification Test. ITC 1982: 183-190 - 1980
- [c11]David J. Lu, Edward J. McCluskey, Masood Namjoo:
Summary of Structural integrity Checking. RTSS 1980: 107-109 - 1978
- [c10]Edward J. McCluskey:
Logic design of multi-valued I2L logic circuits. MVL 1978: 14-22 - 1977
- [c9]John Teets, Charles W. Rose, Edward J. McCluskey:
Panel Discussions. Design Automation and Microprocessors 1977: 110 - 1974
- [c8]Dick B. Simmons, Edward J. McCluskey, Aaron Finerman, Michael L. Dertouzos, Jürg Nievergelt:
University computer curricula. AFIPS National Computer Conference 1974: 1028 - [c7]John F. Wakerly, Edward J. McCluskey:
Design of Low-Cost General-Purpose Self-Diagnosing Computers. IFIP Congress 1974: 108-111 - 1964
- [c6]J. F. Poage, Edward J. McCluskey:
Derivation of optimum test sequences for sequential machines. SWCT 1964: 121-132 - 1963
- [c5]Edward J. McCluskey:
Logical design theory of NOR gate networks with no complemented inputs. SWCT 1963: 137-148 - 1962
- [c4]Edward J. McCluskey:
Reduction of feedback loops in sequential circuits and carry leads in iterative networks. SWCT 1962: 91-102 - [c3]Edward J. McCluskey:
Fundamental Mode and Pulse Mode Operations of Sequential Circuits. IFIP Congress 1962: 725-730 - 1961
- [c2]Edward J. McCluskey:
Minimal sums for Boolean functions having many unspecified fundamental products. SWCT 1961: 10-17 - 1960
- [c1]Ted A. Dolotta, Edward Joseph McCluskey Jr.:
Encoding of incompletely specified Boolean matrices. IRE-AIEE-ACM Computer Conference (Western) 1960: 231-238
Editorship
- 1978
- [e2]Edward J. McCluskey, John F. Wakerly, E. David Crockett, Thomas H. Bredt, David J. Lu, William M. van Cleemput, Susan S. Owicki, Roy C. Ogus, Ravi Apte, M. Danielle Beaurdy, Jacques Losq:
Proceedings of the 5th Annual Symposium on Computer Architecture, Palo Alto, CA, USA, April 1978. ACM 1978, ISBN 978-1-4503-7400-2 - 1972
- [e1]Edward J. McCluskey, Nicholas A. Fortis, Butler W. Lampson, Thomas H. Bredt:
Proceedings of the Third Symposium on Operating System Principles, SOSP 1971, Stanford University, Palo Alto, California, USA, October 18-20, 1971. ACM 1972 [contents]
Coauthor Index
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