Javier D. Bruguera
Javier Diaz Bruguera
Javier D. Bruguera
Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units.
2990-3001
2023
October
72
IEEE Trans. Computers
10
https://doi.org/10.1109/TC.2023.3280136
db/journals/tc/tc72.html#Bruguera23
Javier D. Bruguera
Low-Latency and High-Bandwidth Pipelined Radix-64 Division and Square Root Unit.
10-17
2022
ARITH
https://doi.org/10.1109/ARITH54963.2022.00012
conf/arith/2022
db/conf/arith/arith2022.html#Bruguera22
David M. Russinoff
Javier D. Bruguera
Cuong Chau
Mayank Manjrekar
Nicholas Pfister
Harsha Valsaraju
Formal Verification of a Chained Multiply-Add Design: Combining Theorem Proving and Equivalence Checking.
120-126
2022
ARITH
https://doi.org/10.1109/ARITH54963.2022.00030
conf/arith/2022
db/conf/arith/arith2022.html#RussinoffBCMPV22
Javier D. Bruguera
Low Latency Floating-Point Division and Square Root Unit.
274-287
2020
69
IEEE Trans. Computers
2
https://doi.org/10.1109/TC.2019.2947899
db/journals/tc/tc69.html#Bruguera20
Javier D. Bruguera
Florent de Dinechin
Guest Editors Introduction: Special Section on Computer Arithmetic.
951-952
2019
68
IEEE Trans. Computers
7
https://doi.org/10.1109/TC.2019.2918447
db/journals/tc/tc68.html#BrugueraD19
Javier D. Bruguera
Radix-64 Floating-Point Divider.
84-91
2018
ARITH
https://doi.org/10.1109/ARITH.2018.8464815
https://doi.ieeecomputersociety.org/10.1109/ARITH.2018.8464815
conf/arith/2018
db/conf/arith/arith2018.html#Bruguera18
Neil Burgess
Javier D. Bruguera
Florent de Dinechin
24th IEEE Symposium on Computer Arithmetic, ARITH 2017, London, United Kingdom, July 24-26, 2017
ARITH
IEEE Computer Society
2017
978-1-5386-1965-0
https://ieeexplore.ieee.org/xpl/conhome/8019911/proceeding
https://www.computer.org/csdl/proceedings/arith/2017/1965/00/index.html
db/conf/arith/arith2017.html
Lois Orosa 0001
Javier D. Bruguera
Elisardo Antelo
Asymmetric Allocation in a Shared Flexible Signature Module for Multicore Processors.
1453-1469
2016
59
Comput. J.
10
https://doi.org/10.1093/comjnl/bxw010
db/journals/cj/cj59.html#OrosaBA16
E. G. Paredes
Margarita Amor
Montserrat Bóo
Javier D. Bruguera
Jürgen Döllner
Hybrid terrain rendering based on the external edge primitive.
1095-1116
2016
30
Int. J. Geogr. Inf. Sci.
6
https://doi.org/10.1080/13658816.2015.1105375
db/journals/gis/gis30.html#ParedesABBD16
Daniel Piso Fernandez
Javier D. Bruguera
Obtaining Accurate Error Expressions and Bounds for Floating-Point Multiplicative Algorithms.
319-331
2014
57
Comput. J.
2
https://doi.org/10.1093/comjnl/bxs170
db/journals/cj/cj57.html#FernandezB14
Javier D. Bruguera
Optimizing the representation of intervals.
21-33
2014
90
Sci. Comput. Program.
https://doi.org/10.1016/j.scico.2013.06.002
db/journals/scp/scp90.html#Bruguera14
Álvaro Vázquez
Elisardo Antelo
Javier D. Bruguera
Fast Radix-10 Multiplication Using Redundant BCD Codes.
1902-1914
2014
63
IEEE Trans. Computers
8
https://doi.org/10.1109/TC.2014.2315626
http://doi.ieeecomputersociety.org/10.1109/TC.2014.2315626
db/journals/tc/tc63.html#VazquezAB14
Daniel Piso Fernandez
Javier Diaz Bruguera
A New Rounding Method Based on Parallel Remainder Estimation for Goldschmidt and Newton-Raphson Algorithms.
639-642
2014
DSD
https://doi.org/10.1109/DSD.2014.23
https://doi.ieeecomputersociety.org/10.1109/DSD.2014.23
conf/dsd/2014
db/conf/dsd/dsd2014.html#FernandezB14
Álvaro Vázquez
Javier D. Bruguera
Iterative Algorithm and Architecture for Exponential, Logarithm, Powering, and Root Extraction.
1721-1731
2013
62
IEEE Trans. Computers
9
https://doi.org/10.1109/TC.2012.247
http://doi.ieeecomputersociety.org/10.1109/TC.2012.247
db/journals/tc/tc62.html#VazquezB13
Roberto R. Osorio
Javier D. Bruguera
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard.
119-132
2013
72
J. Signal Process. Syst.
2
https://doi.org/10.1007/s11265-012-0718-y
db/journals/vlsisp/vlsisp72.html#OsorioB13
E. G. Paredes
Montserrat Bóo
Margarita Amor
Javier D. Bruguera
Jürgen Döllner
Extended hybrid meshing algorithm for multiresolution terrain models.
771-793
2012
26
Int. J. Geogr. Inf. Sci.
5
https://doi.org/10.1080/13658816.2011.615317
db/journals/gis/gis26.html#ParedesBABD12
Marc Daumas
Javier D. Bruguera
8th Conference on Real Numbers and Computers.
1-2
2012
216
Inf. Comput.
https://doi.org/10.1016/j.ic.2012.04.001
db/journals/iandc/iandc216.html#DaumasB12
Lois Orosa 0001
Elisardo Antelo
Javier D. Bruguera
FlexSig: Implementing flexible hardware signatures.
30:1-30:20
2012
8
ACM Trans. Archit. Code Optim.
4
https://doi.org/10.1145/2086696.2086709
db/journals/taco/taco8.html#OrosaAB12
E. G. Paredes
Montserrat Bóo
Margarita Amor
Jürgen Döllner
Javier D. Bruguera
GPU-based Visualization of Hybrid Terrain Models.
254-259
2012
GRAPP/IVAPP
conf/grapp/2012
db/conf/grapp/grapp2012.html#ParedesBADB12
https://doi.org/10.5220/0003823302540259
Javier D. Bruguera
Marius Cornea
Debjit Das Sarma
Guest Editors' Introduction: Special Section on Computer Arithmetic.
145-147
2011
60
IEEE Trans. Computers
2
https://doi.org/10.1109/TC.2011.15
http://doi.ieeecomputersociety.org/10.1109/TC.2011.15
db/journals/tc/tc60.html#BrugueraCS11
Daniel Piso Fernandez
Javier D. Bruguera
Variable Latency Goldschmidt Algorithm Based on a New Rounding Method and a Remainder Estimate.
1535-1546
2011
60
IEEE Trans. Computers
11
https://doi.org/10.1109/TC.2010.269
http://doi.ieeecomputersociety.org/10.1109/TC.2010.269
db/journals/tc/tc60.html#FernandezB11
Álvaro Vázquez
Javier D. Bruguera
Composite Iterative Algorithm and Architecture for q-th Root Calculation.
52-61
2011
IEEE Symposium on Computer Arithmetic
https://doi.org/10.1109/ARITH.2011.16
https://doi.ieeecomputersociety.org/10.1109/ARITH.2011.16
conf/arith/2010
db/conf/arith/arith2010.html#VzquezB10
Roberto R. Osorio
Cesar Diaz-Resco
Javier D. Bruguera
High Performance Image Processing on a Massively Parallel Processor Array.
233-236
2009
DSD
https://doi.org/10.1109/DSD.2009.166
https://doi.ieeecomputersociety.org/10.1109/DSD.2009.166
conf/dsd/2009
db/conf/dsd/dsd2009.html#OsorioDB09
Daniel Piso Fernandez
Javier D. Bruguera
Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation.
293-300
2009
DSD
https://doi.org/10.1109/DSD.2009.165
https://doi.ieeecomputersociety.org/10.1109/DSD.2009.165
conf/dsd/2009
db/conf/dsd/dsd2009.html#FernandezB09
Javier D. Bruguera
Marius Cornea
Debjit Das Sarma
John Harrison 0001
19th IEEE Symposium on Computer Arithmetic, ARITH 2009, Portland, Oregon, USA, 9-10 June 2009
978-0-7695-3670-5
IEEE Symposium on Computer Arithmetic
IEEE Computer Society
2009
https://ieeexplore.ieee.org/xpl/conhome/5223291/proceeding
http://www.computer.org/csdl/proceedings/arith/2009/3670/00/index.html
db/conf/arith/arith2009.html
Alex Piñeiro
Javier D. Bruguera
Fabrizio Lamberti
Paolo Montuschi
A Radix-2 Digit-by-Digit Architecture for Cube Root.
562-566
2008
57
IEEE Trans. Computers
4
https://doi.org/10.1109/TC.2007.70848
http://doi.ieeecomputersociety.org/10.1109/TC.2007.70848
https://www.wikidata.org/entity/Q60350156
db/journals/tc/tc57.html#PineiroBLM08
Daniel Piso Fernandez
Javier D. Bruguera
Forcing one-sided results in Goldschmidt algorithm.
1830-1833
2008
ACSCC
https://doi.org/10.1109/ACSSC.2008.5074743
conf/acssc/2008
db/conf/acssc/acssc2008.html#FernandezB08
Roberto R. Osorio
Javier D. Bruguera
An FPGA architecture for CABAC decoding in manycore systems.
293-298
2008
ASAP
https://doi.org/10.1109/ASAP.2008.4580194
https://doi.ieeecomputersociety.org/10.1109/ASAP.2008.4580194
conf/asap/2008
db/conf/asap/asap2008.html#OsorioB08
Daniel Piso Fernandez
Javier D. Bruguera
A New Rounding Algorithm for Variable Latency Division and Square Root Implementations.
760-767
2008
DSD
https://doi.org/10.1109/DSD.2008.28
https://doi.ieeecomputersociety.org/10.1109/DSD.2008.28
conf/dsd/2008
db/conf/dsd/dsd2008.html#PisoB08
Hans-Joachim Bungartz
Javier D. Bruguera
Peter Arbenz
Bruce Hendrickson
Topic 10: Parallel Numerical Algorithms.
778-779
2008
Euro-Par
https://doi.org/10.1007/978-3-540-85451-7_82
conf/europar/2008
db/conf/europar/europar2008.html#BungartzBAH08
F. J. Espino
Montserrat Bóo
Margarita Amor
Javier D. Bruguera
Hardware support for adaptive tessellation of Bézier surfaces based on local tests.
233-250
2007
53
J. Syst. Archit.
4
db/journals/jsa/jsa53.html#EspinoBAB07
https://doi.org/10.1016/j.sysarc.2006.10.011
Paolo Montuschi
Javier D. Bruguera
Luigi Ciminiera
José-Alejandro Piñeiro
A Digit-by-Digit Algorithm for mth Root Extraction.
1696-1706
2007
56
IEEE Trans. Computers
12
https://doi.org/10.1109/TC.2007.70764
https://doi.ieeecomputersociety.org/10.1109/TC.2007.70764
https://www.wikidata.org/entity/Q60350160
db/journals/tc/tc56.html#MontuschiBCP07
Roberto R. Osorio
Javier D. Bruguera
Entropy Coding on a Programmable Processor Array for Multimedia SoC.
222-227
2007
ASAP
https://doi.org/10.1109/ASAP.2007.4429984
https://doi.ieeecomputersociety.org/10.1109/ASAP.2007.4429984
conf/asap/2007
db/conf/asap/asap2007.html#OsorioB07
Roberto R. Osorio
Javier D. Bruguera
High-Throughput Architecture for H.264/AVC CABAC Compression System.
1376-1384
2006
16
IEEE Trans. Circuits Syst. Video Technol.
11
https://doi.org/10.1109/TCSVT.2006.883508
db/journals/tcsv/tcsv16.html#OsorioB06
Viay Holimath
Javier D. Bruguera
A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table.
236-239
2006
conf/dsd/2006
DSD
https://doi.org/10.1109/DSD.2006.97
https://doi.ieeecomputersociety.org/10.1109/DSD.2006.97
db/conf/dsd/dsd2006.html#HolimathB06
Roberto R. Osorio
Javier D. Bruguera
A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems.
269-274
2006
conf/dsd/2006
DSD
https://doi.org/10.1109/DSD.2006.5
https://doi.ieeecomputersociety.org/10.1109/DSD.2006.5
db/conf/dsd/dsd2006.html#OsorioB06
Javier D. Bruguera
Roberto R. Osorio
A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization.
407-414
2006
conf/dsd/2006
DSD
https://doi.org/10.1109/DSD.2006.18
https://doi.ieeecomputersociety.org/10.1109/DSD.2006.18
db/conf/dsd/dsd2006.html#BrugueraO06
José-Alejandro Piñeiro
Stuart F. Oberman
Jean-Michel Muller
Javier D. Bruguera
High-Speed Function Approximation Using a Minimax Quadratic Interpolator.
304-318
2005
54
IEEE Trans. Computers
3
https://doi.org/10.1109/TC.2005.52
http://doi.ieeecomputersociety.org/10.1109/TC.2005.52
db/journals/tc/tc54.html#PineiroOMB05
José-Alejandro Piñeiro
Milos D. Ercegovac
Javier D. Bruguera
High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation.
109-123
2005
40
J. VLSI Signal Process.
1
https://doi.org/10.1007/s11265-005-4941-7
db/journals/vlsisp/vlsisp40.html#PineiroEB05
Javier D. Bruguera
Tomás Lang
Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition.
42-51
2005
conf/arith/2005
IEEE Symposium on Computer Arithmetic
https://doi.org/10.1109/ARITH.2005.22
https://doi.ieeecomputersociety.org/10.1109/ARITH.2005.22
db/conf/arith/arith2005.html#BrugueraL05
Roberto R. Osorio
Javier D. Bruguera
A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder.
298-305
2005
conf/dsd/2005
DSD
https://doi.org/10.1109/DSD.2005.9
https://doi.ieeecomputersociety.org/10.1109/DSD.2005.9
db/conf/dsd/dsd2005.html#OsorioB05
F. J. Espino
Montserrat Bóo
Margarita Amor
Javier D. Bruguera
Adaptive Tessellation of Bezier Surfaces Based on Displacement Maps.
29-32
2005
conf/wscg/2005
WSCG (Short Papers)
db/conf/wscg/wscg2005.html#EspinoBAB05
Tomás Lang
Javier D. Bruguera
Floating-Point Multiply-Add-Fused with Reduced Latency.
988-1003
2004
53
IEEE Trans. Computers
8
https://doi.org/10.1109/TC.2004.44
http://doi.ieeecomputersociety.org/10.1109/TC.2004.44
db/journals/tc/tc53.html#LangB04
José-Alejandro Piñeiro
Milos D. Ercegovac
Javier D. Bruguera
Algorithm and Architecture for Logarithm, Exponential, and Powering Computation.
1085-1096
2004
53
IEEE Trans. Computers
9
https://doi.org/10.1109/TC.2004.53
http://doi.ieeecomputersociety.org/10.1109/TC.2004.53
db/journals/tc/tc53.html#PineiroEB04
Roberto R. Osorio
Javier D. Bruguera
Arithmetic Coding Architecture for H.264/AVC CABAC Compression System.
62-69
2004
conf/dsd/2004
DSD
https://doi.org/10.1109/DSD.2004.1333259
https://doi.ieeecomputersociety.org/10.1109/DSD.2004.1333259
db/conf/dsd/dsd2004.html#OsorioB04
Paula N. Mallón
Montserrat Bóo
Margarita Amor
Javier D. Bruguera
Algorithms and Hardware for Data Compression in Point Rendering Applications.
173-180
2004
conf/wscg/2004
WSCG (Short Papers)
db/conf/wscg/wscg2004.html#MallonBAB04
Juan Touriño
Jorge Parapar
Ramon Doallo
Marcos Boullón
Francisco F. Rivera
Javier D. Bruguera
Xesús P. González
Rafael Crecente
Carlos Álvarez
Research Article: A GIS-embedded system to support land consolidation plans in Galicia.
377-396
2003
17
Int. J. Geogr. Inf. Sci.
4
https://doi.org/10.1080/1365881031000072636
db/journals/gis/gis17.html#TourinoPDBRBGCA03
Daniel Piso Fernandez
José-Alejandro Piñeiro
Javier D. Bruguera
Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor.
543-555
2003
49
J. Syst. Archit.
12-15
https://doi.org/10.1016/S1383-7621(03)00100-0
db/journals/jsa/jsa49.html#PisoPB03
María J. Martín
David E. Singh
José Carlos Mouriño
Francisco F. Rivera
Ramon Doallo
Javier D. Bruguera
High performance air pollution modeling for a power plant environment.
1763-1790
2003
29
Parallel Comput.
11-12
https://doi.org/10.1016/j.parco.2003.05.018
db/journals/pc/pc29.html#MartinSMRDB03
Javier D. Bruguera
Tomás Lang
Multilevel Reverse-Carry Addition: Single and Dual Adders.
55-74
2003
33
J. VLSI Signal Process.
1-2
https://doi.org/10.1023/A:1021141818191
db/journals/vlsisp/vlsisp33.html#BrugueraL03
José-Alejandro Piñeiro
Milos D. Ercegovac
Javier D. Bruguera
High-Radix Iterative Algorithm for Powering Computation.
204-211
2003
conf/arith/2003
IEEE Symposium on Computer Arithmetic
https://doi.org/10.1109/ARITH.2003.1207680
https://doi.ieeecomputersociety.org/10.1109/ARITH.2003.1207680
db/conf/arith/arith2003.html#PineiroEB03
José-Alejandro Piñeiro
Javier D. Bruguera
Milos D. Ercegovac
On-line high-radix exponential with selection by rounding.
121-124
2003
conf/iscas/2003
ISCAS (4)
https://doi.org/10.1109/ISCAS.2003.1205788
db/conf/iscas/iscas2003-4.html#PineiroBE03
F. J. Espino
Montserrat Bóo
Margarita Amor
Javier D. Bruguera
Adaptive Tessellation of NURBS Surfaces.
2003
conf/wscg/2003
WSCG
http://wscg.zcu.cz/wscg2003/Papers_2003/H19.pdf
db/conf/wscg/wscg2003.html#EspinoBAB03
José-Alejandro Piñeiro
Javier D. Bruguera
High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root.
1377-1388
2002
51
IEEE Trans. Computers
12
https://doi.org/10.1109/TC.2002.1146704
http://doi.ieeecomputersociety.org/10.1109/TC.2002.1146704
db/journals/tc/tc51.html#PineiroB02
Paula N. Mallón
Montserrat Bóo
Margarita Amor
Javier D. Bruguera
Concentric Strips: Algorithms and Architecture for the Compression/Decompression of Triangle Meshes.
380-383
2002
conf/3dpvt/2002
3DPVT
https://doi.org/10.1109/TDPVT.2002.1024087
https://doi.ieeecomputersociety.org/10.1109/TDPVT.2002.1024087
db/conf/3dpvt/3dpvt2002.html#MallonBAB02
José-Alejandro Piñeiro
Milos D. Ercegovac
Javier D. Bruguera
High-Radix Logarithm with Selection by Rounding.
101-110
2002
conf/asap/2002
ASAP
https://doi.org/10.1109/ASAP.2002.1030708
https://doi.ieeecomputersociety.org/10.1109/ASAP.2002.1030708
db/conf/asap/asap2002.html#PineiroEB02
Daniel Piso Fernandez
José-Alejandro Piñeiro
Javier D. Bruguera
Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor.
218-225
2002
conf/dsd/2002
DSD
https://doi.org/10.1109/DSD.2002.1115372
https://doi.ieeecomputersociety.org/10.1109/DSD.2002.1115372
db/conf/dsd/dsd2002.html#PisoPB02
Ángel del Río
Montserrat Bóo
Margarita Amor
Javier D. Bruguera
Hardware Implementation of the Subdivision Loop Algorithm.
189-199
2002
conf/euromicro/2002
EUROMICRO
https://doi.org/10.1109/EURMIC.2002.1046156
https://doi.ieeecomputersociety.org/10.1109/EURMIC.2002.1046156
db/conf/euromicro/euromicro2002.html#RioBAB02
José-Alejandro Piñeiro
Milos D. Ercegovac
Javier D. Bruguera
Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm.
132-137
2002
conf/iccd/2002
ICCD
https://doi.org/10.1109/ICCD.2002.1106760
https://doi.ieeecomputersociety.org/10.1109/ICCD.2002.1106760
db/conf/iccd/iccd2002.html#PineiroEB02
Tomás Lang
Javier D. Bruguera
Floating-Point Fused Multiply-Add with Reduced Latency.
145-
2002
conf/iccd/2002
ICCD
https://doi.org/10.1109/ICCD.2002.1106762
https://doi.ieeecomputersociety.org/10.1109/ICCD.2002.1106762
db/conf/iccd/iccd2002.html#LangB02
Javier D. Bruguera
Tomás Lang
Multilevel reverse most-significant carry computation.
959-962
2001
9
IEEE Trans. Very Large Scale Integr. Syst.
6
https://doi.org/10.1109/92.974909
db/journals/tvlsi/tvlsi9.html#BrugueraL01
José-Alejandro Piñeiro
Javier D. Bruguera
Jean-Michel Muller
Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree.
40-
2001
conf/arith/2001
IEEE Symposium on Computer Arithmetic
https://doi.org/10.1109/ARITH.2001.930102
https://doi.ieeecomputersociety.org/10.1109/ARITH.2001.930102
db/conf/arith/arith2001.html#PineiroBM01
Javier D. Bruguera
Tomás Lang
Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition.
203-210
2001
conf/arith/2001
IEEE Symposium on Computer Arithmetic
https://doi.org/10.1109/ARITH.2001.930120
https://doi.ieeecomputersociety.org/10.1109/ARITH.2001.930120
db/conf/arith/arith2001.html#BrugueraL01
José-Alejandro Piñeiro
Javier D. Bruguera
Jean-Michel Muller
FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation.
262-269
2001
conf/dsd/2001
DSD
https://doi.org/10.1109/DSD.2001.952292
https://doi.ieeecomputersociety.org/10.1109/DSD.2001.952292
db/conf/dsd/dsd2001.html#PineiroBM01
Paula N. Mallón
Montserrat Bóo
Javier D. Bruguera
Implementation of a NURBS to Bézier Conversor with Constant Latency.
213-222
2001
conf/fpl/2001
FPL
https://doi.org/10.1007/3-540-44687-7_22
db/conf/fpl/fpl2001.html#MallonBB01
Juan Touriño
Francisco F. Rivera
Carlos Álvarez
Cesar M. Dans
Jorge Parapar
Ramon Doallo
Marcos Boullón
Javier D. Bruguera
Rafael Crecente
Xesús P. González
COPA: a GIS-based Tool for Land Consolidation Projects.
53-58
2001
conf/gis/2001
ACM-GIS
db/conf/gis/gis2001.html#TourinoRADPDBBCG01
https://doi.org/10.1145/512161.512174
José Carlos Mouriño
David E. Singh
María J. Martín
J. M. Eiroa
Francisco F. Rivera
Ramon Doallo
Javier D. Bruguera
Parallelization of the STEM-II Air Quality Model.
543-546
2001
conf/hpcn/2001
HPCN Europe
https://doi.org/10.1007/3-540-48228-8_56
https://www.wikidata.org/entity/Q61483482
db/conf/hpcn/hpcn2001.html#MourinoSMERDB01
José Carlos Mouriño
María J. Martín
Ramon Doallo
David E. Singh
Francisco F. Rivera
Javier D. Bruguera
The STEM-II Air Quality Model on a Distributed Memory System.
85-92
2001
conf/icppw/2001
ICPP Workshops
https://doi.org/10.1109/ICPPW.2001.951855
https://doi.ieeecomputersociety.org/10.1109/ICPPW.2001.951855
https://www.wikidata.org/entity/Q61483488
db/conf/icppw/icppw2001.html#MourinoMDSRB01
Elisardo Antelo
Tomás Lang
Javier D. Bruguera
Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring.
727-739
2000
49
IEEE Trans. Computers
7
https://doi.org/10.1109/12.863043
http://doi.ieeecomputersociety.org/10.1109/12.863043
db/journals/tc/tc49.html#AnteloLB00
Elisardo Antelo
Tomás Lang
Javier D. Bruguera
Very-High Radix CORDIC Rotation Based on Selection by Rounding.
141-153
2000
25
J. VLSI Signal Process.
2
https://doi.org/10.1023/A:1008119006403
db/journals/vlsisp/vlsisp25.html#AnteloLB00
Paula N. Mallón
Montserrat Bóo
Javier D. Bruguera
Parallel Architecture for Conversion of NURBS Curves to Bézier Curves.
1324-1331
2000
conf/euromicro/2000
EUROMICRO
https://doi.org/10.1109/EURMIC.2000.874649
https://doi.ieeecomputersociety.org/10.1109/EURMIC.2000.874649
db/conf/euromicro/euromicro2000.html#MallonBB00
Roberto R. Osorio
Javier D. Bruguera
Architectures for arithmetic coding in image compression.
1-4
2000
EUSIPCO
https://ieeexplore.ieee.org/document/7075425/
conf/eusipco/2000
db/conf/eusipco/eusipco2000.html#OsorioB00
Javier D. Bruguera
Tomás Lang
Multilevel Reverse-Carry Adder.
155-162
2000
conf/iccd/2000
ICCD
https://doi.org/10.1109/ICCD.2000.878282
https://doi.ieeecomputersociety.org/10.1109/ICCD.2000.878282
db/conf/iccd/iccd2000.html#BrugueraL00
Carlos E. Cabrera Reyes
Javier D. Bruguera
VLSI systolic array architecture for the lattice structure of the discrete wavelet transform.
605-608
2000
ISCAS
https://doi.org/10.1109/ISCAS.2000.858824
conf/iscas/2000
db/conf/iscas/iscas2000.html#ReyesB00
Javier D. Bruguera
Tomás Lang
Leading-One Prediction with Concurrent Position Correction.
1083-1097
1999
48
IEEE Trans. Computers
10
db/journals/tc/tc48.html#BrugueraL99
https://doi.org/10.1109/12.805157
http://doi.ieeecomputersociety.org/10.1109/12.805157
Elisardo Antelo
Tomás Lang
Javier D. Bruguera
Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding.
204-
1999
conf/arith/1999
IEEE Symposium on Computer Arithmetic
https://doi.org/10.1109/ARITH.1999.762846
https://doi.ieeecomputersociety.org/10.1109/ARITH.1999.762846
db/conf/arith/arith1999.html#AnteloLB99
Tomás Lang
Javier D. Bruguera
Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition.
73-79
1999
conf/iccd/1999
ICCD
https://doi.org/10.1109/ICCD.1999.808390
https://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808390
db/conf/iccd/iccd1999.html#LangB99
Roberto R. Osorio
Javier D. Bruguera
New model for arithmetic coding/decoding of multilevel images based on a cache memory.
697-700
1999
ICECS
https://doi.org/10.1109/ICECS.1999.813204
conf/icecsys/1999
db/conf/icecsys/icecsys1999.html#OsorioB99
Elisardo Antelo
Tomás Lang
Javier D. Bruguera
Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling.
152-161
1998
47
IEEE Trans. Computers
2
db/journals/tc/tc47.html#AnteloLB98
https://doi.org/10.1109/12.663761
http://doi.ieeecomputersociety.org/10.1109/12.663761
Elisardo Antelo
Montserrat Bóo
Javier D. Bruguera
Emilio L. Zapata
A novel design of a two operand normalization circuit.
173-176
1998
6
IEEE Trans. Very Large Scale Integr. Syst.
1
https://doi.org/10.1109/92.661260
db/journals/tvlsi/tvlsi6.html#AnteloBBZ98
Julio Villalba
Emilio L. Zapata
Elisardo Antelo
Javier D. Bruguera
Radix-4 Vectoring CORDIC Algorithm and Architectures.
127-147
1998
19
J. VLSI Signal Process.
2
https://doi.org/10.1023/A:1008061701575
db/journals/vlsisp/vlsisp19.html#VillalbaZAB98
Roberto R. Osorio
Montserrat Bóo
Javier D. Bruguera
Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory.
10139-
1998
conf/euromicro/1998
EUROMICRO
https://doi.org/10.1109/EURMIC.1998.711788
https://doi.ieeecomputersociety.org/10.1109/EURMIC.1998.711788
db/conf/euromicro/euromicro1998.html#OsorioBB98
Javier D. Bruguera
Tomás Lang
Leading-one prediction scheme for latency improvement in single datapath floating-point adders.
298-305
1998
conf/iccd/1998
ICCD
https://doi.org/10.1109/ICCD.1998.727065
https://doi.ieeecomputersociety.org/10.1109/ICCD.1998.727065
db/conf/iccd/iccd1998.html#BrugueraL98
Elisardo Antelo
Julio Villalba
Javier D. Bruguera
Emilio L. Zapata
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm.
855-870
1997
46
IEEE Trans. Computers
8
db/journals/tc/tc46.html#AnteloVBZ97
https://doi.org/10.1109/12.609275
http://doi.ieeecomputersociety.org/10.1109/12.609275
Elisardo Antelo
Javier D. Bruguera
Tomás Lang
Emilio L. Zapata
Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm.
1264-1271
1997
46
IEEE Trans. Computers
11
db/journals/tc/tc46.html#AnteloBLZ97
https://doi.org/10.1109/12.644300
http://doi.ieeecomputersociety.org/10.1109/12.644300
Montserrat Bóo
Francisco Argüello
Javier D. Bruguera
Ramon Doallo
Emilio L. Zapata
High-performance VLSI architecture for the Viterbi algorithm.
168-176
1997
45
IEEE Trans. Commun.
2
https://doi.org/10.1109/26.554365
db/journals/tcom/tcom45.html#BooABDZ97
Montserrat Bóo
Francisco Argüello
Javier D. Bruguera
Emilio L. Zapata
Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures.
57-73
1997
17
J. VLSI Signal Process.
1
https://doi.org/10.1023/A:1007949000569
db/journals/vlsisp/vlsisp17.html#BooABZ97
Roberto R. Osorio
Javier D. Bruguera
New arithmetic coder/decoder architectures based on pipelining.
106-115
1997
conf/asap/1997
ASAP
https://doi.org/10.1109/ASAP.1997.606817
https://doi.ieeecomputersociety.org/10.1109/ASAP.1997.606817
db/conf/asap/asap1997.html#OsorioB97
Mercedes Peón
Roberto R. Osorio
Javier D. Bruguera
A VLSI implementation of an arithmetic coder for image compression.
591-
1997
conf/euromicro/1997
EUROMICRO
https://doi.org/10.1109/EURMIC.1997.617380
https://doi.ieeecomputersociety.org/10.1109/EURMIC.1997.617380
db/conf/euromicro/euromicro1997.html#PeonOB97
Carlos Cabrera
Montserrat Bóo
Javier D. Bruguera
VLSI implementation of an area-efficient architecture for the Viterbi algorithm.
623-626
1997
ICASSP
https://doi.org/10.1109/ICASSP.1997.599845
https://doi.ieeecomputersociety.org/10.1109/ICASSP.1997.599845
conf/icassp/1997
db/conf/icassp/icassp1997.html#CabreraBB97
Elisardo Antelo
Javier D. Bruguera
Emilio L. Zapata
Unified Mixed Radix 2-4 Redundant CORDIC Processor.
1068-1073
1996
45
IEEE Trans. Computers
9
db/journals/tc/tc45.html#AnteloBZ96
https://doi.org/10.1109/12.537131
http://doi.ieeecomputersociety.org/10.1109/12.537131
Javier D. Bruguera
Nicolás Guil
Tomás Lang
Julio Villalba
Emilio L. Zapata
Cordic based parallel/pipelined architecture for the Hough transform.
207-221
1996
12
J. VLSI Signal Process.
3
https://doi.org/10.1007/BF00924986
db/journals/vlsisp/vlsisp12.html#BrugueraGLVZ96
Julio Villalba
J. C. Arrabal
Emilio L. Zapata
Elisardo Antelo
Javier D. Bruguera
Radix-4 Vectoring Cordic Algorithm And Architectures.
55-64
1996
conf/asap/1996
ASAP
https://doi.org/10.1109/ASAP.1996.542801
https://doi.ieeecomputersociety.org/10.1109/ASAP.1996.542801
db/conf/asap/asap1996.html#VillalbaAZAB96
Montserrat Bóo
Francisco Argüello
Javier D. Bruguera
Emilio L. Zapata
High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining.
165-
1996
conf/asap/1996
ASAP
https://doi.org/10.1109/ASAP.1996.542811
https://doi.ieeecomputersociety.org/10.1109/ASAP.1996.542811
db/conf/asap/asap1996.html#BooABZ96
Elisardo Antelo
Javier D. Bruguera
Tomás Lang
Julio Villalba
Emilio L. Zapata
High Radix Cordic Rotation Based on Selection by Rounding.
155-164
1996
conf/europar/1996-2
Euro-Par, Vol. II
db/conf/europar/europar96-2.html#AnteloBLVZ96
https://doi.org/10.1007/BFb0024698
Montserrat Bóo
Francisco Argüello
Javier D. Bruguera
Emilio L. Zapata
High performance VLSI architecture for the trellis coded quantization.
995-998
1996
conf/icip/1996
ICIP (2)
https://doi.org/10.1109/ICIP.1996.561073
db/conf/icip/icip1996-2.html#BooABZ96
Francisco Argüello
Javier D. Bruguera
Emilio L. Zapata
A Parallel Architecture for the Self-Sorting FFT Algorithm.
88-97
1995
31
J. Parallel Distributed Comput.
1
https://doi.org/10.1006/jpdc.1995.1147
db/journals/jpdc/jpdc31.html#ArguelloBZ95
Elisardo Antelo
Javier D. Bruguera
Julio Villalba
Emilio L. Zapata
Redundant CORDIC Rotator Based on Parallel Prediction.
172-179
1995
conf/arith/1995
IEEE Symposium on Computer Arithmetic
https://doi.org/10.1109/ARITH.1995.465362
https://doi.ieeecomputersociety.org/10.1109/ARITH.1995.465362
db/conf/arith/arith1995.html#AnteloBVZ95
Roberto R. Osorio
Elisardo Antelo
Javier D. Bruguera
Julio Villalba
Emilio L. Zapata
Digit On-line Large Radix CORDIC Rotator.
246-257
1995
conf/asap/1995
ASAP
https://doi.org/10.1109/ASAP.1995.522929
https://doi.ieeecomputersociety.org/10.1109/ASAP.1995.522929
db/conf/asap/asap1995.html#OsorioABVZ95
Julio Villalba
José Antonio Hidalgo López
Emilio L. Zapata
Elisardo Antelo
Javier D. Bruguera
CORDIC Architectures with Parallel Compensation of the Scale Factor.
258-269
1995
conf/asap/1995
ASAP
https://doi.org/10.1109/ASAP.1995.522930
https://doi.ieeecomputersociety.org/10.1109/ASAP.1995.522930
db/conf/asap/asap1995.html#VillalbaHZAB95
Javier D. Bruguera
Tomás Lang
2-D DCT using on-line arithmetic.
3275-3278
1995
ICASSP
https://doi.org/10.1109/ICASSP.1995.479584
https://doi.ieeecomputersociety.org/10.1109/ICASSP.1995.479584
conf/icassp/1995
db/conf/icassp/icassp1995.html#BrugueraL95
Francisco Argüello
Javier D. Bruguera
Ramon Doallo
Emilio L. Zapata
Parallel Architecture for Fast Transforms with Trigonometric Kernel.
1091-1099
1994
5
IEEE Trans. Parallel Distributed Syst.
10
https://doi.org/10.1109/71.313124
http://doi.ieeecomputersociety.org/10.1109/71.313124
db/journals/tpds/tpds5.html#ArguelloBDZ94
Javier D. Bruguera
Elisardo Antelo
Emilio L. Zapata
Design of a Pipelined Radix 4 CORDIC Processor.
729-744
1993
19
Parallel Comput.
7
db/journals/pc/pc19.html#BrugueraAZ93
https://doi.org/10.1016/0167-8191(93)90061-O
Emilio L. Zapata
Ignacio Benavides
Francisco F. Rivera
Javier D. Bruguera
Tomás F. Pena
José María Carazo
Image reconstruction on hypercube computers: Application to electron microscopy.
51-64
1992
27
Signal Process.
1
https://doi.org/10.1016/0165-1684(92)90111-9
db/journals/sigpro/sigpro27.html#ZapataBRBPC92
Francisco Argüello
Ramon Doallo
Javier D. Bruguera
Emilio L. Zapata
Design of a constant geometry fast Hartley transformer.
1137-1140
1991
ICASSP
https://doi.org/10.1109/ICASSP.1991.150568
conf/icassp/1991
db/conf/icassp/icassp1991.html#ArguelloDBZ91
Oscar G. Plata
Javier D. Bruguera
Francisco F. Rivera
Ramon Doallo
Emilio L. Zapata
ACLE: A Software Package for SIMD Computer Simulation.
194-203
1990
33
Comput. J.
3
db/journals/cj/cj33.html#PlataBRDZ90
https://doi.org/10.1093/comjnl/33.3.194
Javier D. Bruguera
Emilio L. Zapata
Oscar G. Plata
A reliability model for multiprocessor networks with degradable nodes.
15-25
1990
29
Microprocessing and Microprogramming
1
https://doi.org/10.1016/0165-6074(90)90008-W
db/journals/jsa/jsa29.html#BrugueraZP90
Emilio L. Zapata
Francisco Argüello
Francisco Fernandez Rivera
Javier D. Bruguera
Multidimensional fast Hartley transform onto SIMD hypercubes.
121-134
1990
29
Microprocessing and Microprogramming
2
https://doi.org/10.1016/0165-6074(90)90329-8
db/journals/jsa/jsa29.html#ZapataARB90
Francisco F. Rivera
Ramon Doallo
Javier D. Bruguera
Emilio L. Zapata
Richard L. Peskin
Gaussian elimination with pivoting on hypercubes.
51-60
1990
14
Parallel Comput.
1
db/journals/pc/pc14.html#RiveraDBZP90
https://doi.org/10.1016/0167-8191(90)90095-Q
Inmaculada García
Juan Julián Merelo Guervós
Javier D. Bruguera
Emilio L. Zapata
Parallel quadrant interlocking factorization on hypercube computers.
87-100
1990
15
Parallel Comput.
1-3
db/journals/pc/pc15.html#GarciaMBZ90
https://doi.org/10.1016/0167-8191(90)90033-6
Emilio L. Zapata
Javier D. Bruguera
Oscar G. Plata
Francisco F. Rivera
A parallel markovian model reliability algorithm for hypercube networks.
501-508
1989
27
Microprocessing and Microprogramming
1-5
https://doi.org/10.1016/0165-6074(89)90099-9
db/journals/jsa/jsa27.html#ZapataBPR89
Carlos Álvarez
Margarita Amor
Elisardo Antelo
Peter Arbenz
Francisco Argüello
J. C. Arrabal
José Ignacio Benavides BenítezIgnacio Benavides
Montserrat Bóo
Marcos Boullón-MagánMarcos Boullón
Hans-Joachim Bungartz
Neil Burgess
Carlos Cabrera
José María Carazo
Cuong Chau
Luigi Ciminiera
Marius Cornea
Rafael Crecente-MasedaRafael Crecente
Cesar M. Dans
Marc Daumas
Cesar Diaz-Resco
Florent de Dinechin
Ramón DoalloRamon Doallo
Jürgen Döllner
J. M. Eiroa
Milos D. Ercegovac
F. J. Espino
Daniel Piso Fernandez
Inmaculada García
Xesús P. González
Juan Julián Merelo Guervós
Nicolás Guil
John Harrison 0001
Bruce Hendrickson
José A. Hidalgo-LópezJosé Antonio Hidalgo López
Viay Holimath
Fabrizio Lamberti
Tomás Lang
Paula N. Mallón
Mayank Manjrekar
María J. Martín
Paolo Montuschi
José Carlos Mouriño
Jean-Michel Muller
Stuart F. Oberman
Lois Orosa 0001
Roberto R. Osorio
Jorge Parapar
E. G. Paredes
Tomás F. Pena
Mercedes Peón
Richard L. Peskin
Nicholas Pfister
Alex Piñeiro
José-Alejandro Piñeiro
Oscar G. Plata
Carlos E. Cabrera Reyes
Ángel del Río
Francisco F. RiveraFrancisco Fernandez Rivera
David M. Russinoff
Debjit Das Sarma
David E. Singh
Juan Touriño
Harsha Valsaraju
Álvaro Vázquez
Julio Villalba
Emilio L. Zapata