Paul Chow
University of Toronto, Canada
http://www.eecg.utoronto.ca/~pc/
https://dl.acm.org/profile/81322491286
https://orcid.org/0000-0002-0523-7117
https://www.wikidata.org/entity/Q122782853
https://scholar.google.com/citations?user=FPrWBAoAAAAJ
Mohammad Ewais
Paul Chow
DDC: A Vision for a Disaggregated Datacenter.
2024
abs/2402.12742
CoRR
https://doi.org/10.48550/arXiv.2402.12742
db/journals/corr/corr2402.html#abs-2402-12742
Mohammad Ewais
Paul Chow
Disaggregated Memory in the Datacenter: A Survey.
20688-20712
2023
11
IEEE Access
https://doi.org/10.1109/ACCESS.2023.3250407
db/journals/access/access11.html#EwaisC23
Mohammadmahdi Mazraeli
Yu Gao
Paul Chow
Partitioning Large-Scale, Multi-FPGA Applications for the Data Center.
253-258
2023
FPL
https://doi.org/10.1109/FPL60245.2023.00043
conf/fpl/2023
db/conf/fpl/fpl2023.html#MazraeliGC23
Qianfeng Shen
Jun Zheng
Paul Chow
RIFL: A Reliable Link Layer Network Protocol for Data Center Communication.
2023
abs/2309.08696
CoRR
https://doi.org/10.48550/arXiv.2309.08696
db/journals/corr/corr2309.html#abs-2309-08696
Qianfeng Shen
Paul Chow
A Lightweight Routing Layer Using a Reliable Link-Layer Protocol.
2023
abs/2311.00911
CoRR
https://doi.org/10.48550/arXiv.2311.00911
db/journals/corr/corr2311.html#abs-2311-00911
Qianfeng Shen
Jun Zheng
Paul Chow
RIFL: a reliable link layer network protocol for data center communication.
111-126
2022
14
JOCN
3
https://doi.org/10.1364/jocn.443448
db/journals/jocnet/jocnet14.html#ShenZC22
Naif Tarafdar
Giuseppe Di Guglielmo
Philip C. Harris
Jeffrey D. Krupa
Vladimir Loncar
Dylan S. Rankin
Nhan Tran
Zhenbin Wu
Qianfeng Shen
Paul Chow
AIgean: An Open Framework for Deploying Machine Learning on Heterogeneous Clusters.
23:1-23:32
2022
15
ACM Trans. Reconfigurable Technol. Syst.
3
https://doi.org/10.1145/3482854
db/journals/trets/trets15.html#TarafdarGHKLRTW22
Christophe Bobda
Joel Mandebi Mbongue
Paul Chow
Mohammad Ewais
Naif Tarafdar
Juan Camilo Vega
Ken Eguro
Dirk Koch
Suranga Handagala
Miriam Leeser
Martin C. Herbordt
Hafsah Shahzad
H. Peter Hofstee
Burkhard Ringlein
Jakub Szefer
Ahmed Sanaullah
Russell Tessier
The Future of FPGA Acceleration in Datacenters and the Cloud.
34:1-34:42
2022
15
ACM Trans. Reconfigurable Technol. Syst.
3
https://doi.org/10.1145/3506713
db/journals/trets/trets15.html#BobdaMCETVEKHLH22
Qianfeng Clark Shen
Juan Camilo Vega
Paul Chow
Parallel CRC On An FPGA At Terabit Speeds.
1-6
2022
FPT
https://doi.org/10.1109/ICFPT56656.2022.9974233
conf/fpt/2022
db/conf/fpt/icfpt2022.html#ShenVC22
Jun Li 0094
Paul Chow
Yuanxi Peng
Tian Jiang
FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction.
259-272
2021
29
IEEE Trans. Very Large Scale Integr. Syst.
2
https://doi.org/10.1109/TVLSI.2020.3030906
db/journals/tvlsi/tvlsi29.html#LiCPJ21
Juan Camilo Vega
Mohammad Ewais
Alberto Leon-Garcia
Paul Chow
FFIVE: An FPGA Framework for Interactive VNF Environments.
263
2021
FCCM
https://doi.org/10.1109/FCCM51124.2021.00050
conf/fccm/2021
db/conf/fccm/fccm2021.html#VegaELC21
Arzhang Rafii
Paul Chow
Welson Sun
Pharos: a Performance Monitor for Multi-FPGA Systems.
271
2021
FCCM
https://doi.org/10.1109/FCCM51124.2021.00056
conf/fccm/2021
db/conf/fccm/fccm2021.html#RafiiCS21
Marco Antonio Merlini
Isamu Poy
Paul Chow
Interactive Debugging at IP Block Interfaces in FPGAs.
138-144
2021
FPGA
https://doi.org/10.1145/3431920.3439305
conf/fpga/2021
db/conf/fpga/fpga2021.html#MerliniPC21
Qianfeng Clark Shen
Jun Zheng
Paul Chow
RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPGA Communication.
148
2021
FPGA
https://doi.org/10.1145/3431920.3439467
conf/fpga/2021
db/conf/fpga/fpga2021.html#ShenZC21
Varun Sharma
Paul Chow
Exploring PGAS Communication for Heterogeneous Clusters with FPGAs.
225
2021
FPGA
https://doi.org/10.1145/3431920.3439469
conf/fpga/2021
db/conf/fpga/fpga2021.html#SharmaC21
Arzhang Rafii
Welson Sun
Paul Chow
Pharos: a Multi-FPGA Performance Monitor.
257-262
2021
FPL
https://doi.org/10.1109/FPL53798.2021.00048
conf/fpl/2021
db/conf/fpl/fpl2021.html#RafiiSC21
Mohammad Ewais
Juan Camilo Vega
Alberto Leon-Garcia
Paul Chow
A Framework Integrating FPGAs in VNF Networks.
1-9
2021
NoF
https://doi.org/10.1109/NoF52522.2021.9609941
conf/nof/2021
db/conf/nof/nof2021.html#EwaisVLC21
Christian Plessl
Paul Chow
Marco Platzner
HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Virtual Event, Germany, 21-23 June, 2021.
ACM
HEART
2021
978-1-4503-8549-7
https://doi.org/10.1145/3468044
db/conf/heart/heart2021.html
Varun Sharma
Paul Chow
A PGAS Communication Library for Heterogeneous Clusters.
2021
abs/2104.12350
CoRR
https://arxiv.org/abs/2104.12350
db/journals/corr/corr2104.html#abs-2104-12350
Juan Camilo Vega
Marco Antonio Merlini
Paul Chow
FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark.
47-55
2020
FCCM
https://doi.org/10.1109/FCCM48280.2020.00016
conf/fccm/2020
db/conf/fccm/fccm2020.html#VegaMC20
Charles Lo
Paul Chow
Hierarchical Modelling of Generators in Design-Space Exploration.
186-194
2020
FCCM
https://doi.org/10.1109/FCCM48280.2020.00033
conf/fccm/2020
db/conf/fccm/fccm2020.html#LoC20
Juan Camilo Vega
Qianfeng Clark Shen
Paul Chow
SHIP: Storage for Hybrid Interconnected Processors.
211
2020
FCCM
https://doi.org/10.1109/FCCM48280.2020.00043
conf/fccm/2020
db/conf/fccm/fccm2020.html#VegaSC20
Naif Tarafdar
Giuseppe Di Guglielmo
Philip C. Harris
Jeffrey D. Krupa
Vladimir Loncar
Dylan S. Rankin
Nhan Tran
Zhenbin Wu
Qianfeng Shen
Paul Chow
AIgean: An Open Framework for Machine Learning on Heterogeneous Clusters.
239
2020
FCCM
https://doi.org/10.1109/FCCM48280.2020.00072
conf/fccm/2020
db/conf/fccm/fccm2020.html#TarafdarGHKLRTW20
Ehsan Ghasemi
Paul Chow
Accelerating Apache Spark with FPGAs.
2019
31
Concurr. Comput. Pract. Exp.
2
https://doi.org/10.1002/cpe.4222
db/journals/concurrency/concurrency31.html#GhasemiC19
Varun Sharma
Naif Tarafdar
Paul Chow
Sonar: Writing Testbenches through Python.
311
2019
FCCM
https://doi.org/10.1109/FCCM.2019.00052
conf/fccm/2019
db/conf/fccm/fccm2019.html#SharmaTC19
Daniel Rozhko
Paul Chow
The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs.
232-241
2019
FPGA
https://doi.org/10.1145/3289602.3293903
conf/fpga/2019
db/conf/fpga/fpga2019.html#RozhkoC19
Nariman Eskandari
Naif Tarafdar
Daniel Ly-Ma
Paul Chow
A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center.
262-271
2019
FPGA
https://doi.org/10.1145/3289602.3293909
conf/fpga/2019
db/conf/fpga/fpga2019.html#EskandariTLC19
Juan Camilo Vega
Qianfeng Shen
Alberto Leon-Garcia
Paul Chow
Introducing ReCPRI: A Field Re-configurable Protocol for Backhaul Communication in a Radio Access Network.
2019
IM
http://dl.ifip.org/db/conf/im/im2019/189399.pdf
https://ieeexplore.ieee.org/document/8717902
conf/im/2019
db/conf/im/im2019.html#VegaSLC19
329-336
Naif Tarafdar
Nariman Eskandari
Thomas Lin
Paul Chow
Designing for FPGAs in the Cloud.
23-29
2018
35
IEEE Des. Test
1
https://doi.org/10.1109/MDAT.2017.2748393
db/journals/dt/dt35.html#TarafdarELC18
Naif Tarafdar
Nariman Eskandari
Varun Sharma
Charles Lo
Paul Chow
Galapagos: A Full Stack Approach to FPGA Integration in the Cloud.
18-24
2018
38
IEEE Micro
6
https://doi.org/10.1109/MM.2018.2877290
http://doi.ieeecomputersociety.org/10.1109/MM.2018.2877290
db/journals/micro/micro38.html#TarafdarESLC18
Abdul-Amir Yassine
Yasmin Afsharnejad
Omar Ragheb
Vaughn Betz
Paul Chow
A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media.
216
2018
FCCM
https://doi.org/10.1109/FCCM.2018.00050
https://doi.ieeecomputersociety.org/10.1109/FCCM.2018.00050
conf/fccm/2018
db/conf/fccm/fccm2018.html#YassineARBC18
Charles Lo
Paul Chow
Multi-fidelity Optimization for High-Level Synthesis Directives.
272-279
2018
FPL
https://doi.org/10.1109/FPL.2018.00054
https://doi.ieeecomputersociety.org/10.1109/FPL.2018.00054
conf/fpl/2018
db/conf/fpl/fpl2018.html#LoC18
Yasmin Afsharnejad
Abdul-Amir Yassine
Omar Ragheb
Paul Chow
Vaughn Betz
HLS-based FPGA Acceleration of Light Propagation Simulation in Turbid Media.
11:1-11:6
2018
HEART
https://doi.org/10.1145/3241793.3241804
conf/heart/2018
db/conf/heart/heart2018.html#AfsharnejadYRCB18
Thomas Lin
Naif Tarafdar
Byungchul Park
Paul Chow
Alberto Leon-Garcia
Enabling network function virtualization over heterogeneous resources.
58-63
2017
APNOMS
https://doi.org/10.1109/APNOMS.2017.8094179
conf/apnoms/2017
db/conf/apnoms/apnoms2017.html#LinTPCL17
Paul Chow
Building the Reconfigurable Cloud Ecosystem.
10:1
2017
ETCD@ASPLOS
https://doi.org/10.1145/3129457.3129501
conf/asplos/2017etcd
db/conf/asplos/etcd2017.html#Chow17
Daniel Rozhko
Geoffrey Elliott
Daniel Ly-Ma
Paul Chow
Hans-Arno Jacobsen
Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules.
201-206
2017
FPGA
http://dl.acm.org/citation.cfm?id=3021752
conf/fpga/2017
db/conf/fpga/fpga2017.html#RozhkoELCJ17
Naif Tarafdar
Thomas Lin
Eric Fukuda
Hadi Bannazadeh
Alberto Leon-Garcia
Paul Chow
Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center.
237-246
2017
FPGA
http://dl.acm.org/citation.cfm?id=3021742
conf/fpga/2017
db/conf/fpga/fpga2017.html#TarafdarLFBLC17
Naif Tarafdar
Thomas Lin
Nariman Eskandari
David Lion
Alberto Leon-Garcia
Paul Chow
Heterogeneous virtualized network function framework for the data center.
1-8
2017
FPL
https://doi.org/10.23919/FPL.2017.8056790
conf/fpl/2017
db/conf/fpl/fpl2017.html#TarafdarLELLC17
Zhiqiang Liu
Yong Dou
Jingfei Jiang
Qiang Wang 0006
Paul Chow
An FPGA-based processor for training convolutional neural networks.
207-210
2017
FPT
https://doi.org/10.1109/FPT.2017.8280142
conf/fpt/2017
db/conf/fpt/fpt2017.html#LiuDJ0C17
Roberto DiCecco
Lin Sun
Paul Chow
FPGA-based training of convolutional neural networks with a reduced precision floating-point library.
239-242
2017
FPT
https://doi.org/10.1109/FPT.2017.8280150
conf/fpt/2017
db/conf/fpt/fpt2017.html#DiCeccoSC17
Vincent Mirian
Paul Chow
Enabling FPGAs as a True Device in the OpenCL Standard: Bridging the Gap for FPGAs.
5:1-5:12
2017
IWOCL
https://doi.org/10.1145/3078155.3078176
conf/iwocl/2017
db/conf/iwocl/iwocl2017.html#MirianC17
Fernando Martin del Campo
Paul Chow
Task replication and control for highly parallel in-memory stores.
312-326
2017
MEMSYS
https://doi.org/10.1145/3132402.3132428
conf/memsys/2017
db/conf/memsys/memsys2017.html#CampoC17
Andrew Boutros
Brett Grady
Mustafa Abbas
Paul Chow
Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis.
1-6
2017
ReConFig
https://doi.org/10.1109/RECONFIG.2017.8279781
conf/reconfig/2017
db/conf/reconfig/reconfig2017.html#BoutrosGAC17
Jianfeng Zhang
Paul Chow
Hengzhu Liu
CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition.
9:1-9:22
2016
9
ACM Trans. Reconfigurable Technol. Syst.
2
https://doi.org/10.1145/2827700
db/journals/trets/trets9.html#ZhangCL16
Ehsan Ghasemi
Paul Chow
Accelerating Apache Spark Big Data Analysis with FPGAs.
94
2016
FCCM
https://doi.org/10.1109/FCCM.2016.33
https://doi.ieeecomputersociety.org/10.1109/FCCM.2016.33
conf/fccm/2016
db/conf/fccm/fccm2016.html#GhasemiC16
Ehsan Ghasemi
Paul Chow
A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only).
274
2016
FPGA
https://doi.org/10.1145/2847263.2847294
conf/fpga/2016
db/conf/fpga/fpga2016.html#GhasemiC16
Charles Lo
Paul Chow
Model-based optimization of High Level Synthesis directives.
1-10
2016
FPL
https://doi.org/10.1109/FPL.2016.7577358
conf/fpl/2016
db/conf/fpl/fpl2016.html#LoC16
Roberto DiCecco
Griffin Lacey
Jasmina Vasiljevic
Paul Chow
Graham W. Taylor
Shawki Areibi
Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks.
265-268
2016
FPT
https://doi.org/10.1109/FPT.2016.7929549
conf/fpt/2016
db/conf/fpt/fpt2016.html#DiCeccoLVCTA16
Vincent Mirian
Paul Chow
Extracting Designs of Secure IPs Using FPGA CAD Tools.
293-298
2016
ACM Great Lakes Symposium on VLSI
https://doi.org/10.1145/2902961.2903033
conf/glvlsi/2016
db/conf/glvlsi/glvlsi2016.html#MirianC16
Ehsan Ghasemi
Paul Chow
Accelerating Apache Spark Big Data Analysis with FPGAs.
737-744
2016
UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld
https://doi.org/10.1109/UIC-ATC-ScalCom-CBDCom-IoP-SmartWorld.2016.0119
https://doi.ieeecomputersociety.org/10.1109/UIC-ATC-ScalCom-CBDCom-IoP-SmartWorld.2016.0119
conf/uic/2016
db/conf/uic/uic2016.html#GhasemiC16
Roberto DiCecco
Griffin Lacey
Jasmina Vasiljevic
Paul Chow
Graham W. Taylor
Shawki Areibi
Caffeinated FPGAs: FPGA Framework For Convolutional Neural Networks.
2016
abs/1609.09671
CoRR
http://arxiv.org/abs/1609.09671
db/journals/corr/corr1609.html#DiCeccoLVCTA16
Jianfeng Zhang
Paul Chow
Hengzhu Liu
An Enhanced Adaptive Recoding Rotation CORDIC.
4:1-4:25
2015
9
ACM Trans. Reconfigurable Technol. Syst.
1
https://doi.org/10.1145/2812813
db/journals/trets/trets9.html#ZhangCL15
Stuart Byma
Naif Tarafdar
Talia Xu
Hadi Bannazadeh
Alberto Leon-Garcia
Paul Chow
Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware.
94-97
2015
FPGA
https://doi.org/10.1145/2684746.2689086
conf/fpga/2015
db/conf/fpga/fpga2015.html#BymaTXBLC15
Jasmina Vasiljevic
Ralph Wittig
Paul Schumacher
Jeff Fifield
Fernando Martinez-Vallina
Henry Styles
Paul Chow
OpenCL library of stream memory components targeting FPGAs.
104-111
2015
FPT
https://doi.org/10.1109/FPT.2015.7393134
conf/fpt/2015
db/conf/fpt/fpt2015.html#VasiljevicWSFMS15
Vincent Mirian
Paul Chow
Exploring pipe implementations using an OpenCL framework for FPGAs.
112-119
2015
FPT
https://doi.org/10.1109/FPT.2015.7393135
conf/fpt/2015
db/conf/fpt/fpt2015.html#MirianC15
Jianfeng Zhang
Paul Chow
Hengzhu Liu
FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC.
128-135
2015
FPT
https://doi.org/10.1109/FPT.2015.7393139
conf/fpt/2015
db/conf/fpt/fpt2015.html#ZhangCL15
Fernando Martin del Campo
Paul Chow
Architecture Exploration for Data Intensive Applications.
135-145
2015
MEMSYS
https://doi.org/10.1145/2818950.2818970
conf/memsys/2015
db/conf/memsys/memsys2015.html#CampoC15
Vincent Mirian
Paul Chow
Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs.
1-8
2015
ReConFig
https://doi.org/10.1109/ReConFig.2015.7393303
conf/reconfig/2015
db/conf/reconfig/reconfig2015.html#MirianC15
Vincent Mirian
Paul Chow
UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAs.
1-6
2015
ReConFig
https://doi.org/10.1109/ReConFig.2015.7393366
conf/reconfig/2015
db/conf/reconfig/reconfig2015.html#MirianC15a
Yuanxi Peng
Manuel Saldaña
Christopher A. Madill
Xiaofeng Zou
Paul Chow
Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications.
17:1-17:23
2014
7
ACM Trans. Reconfigurable Technol. Syst.
3
https://doi.org/10.1145/2629470
db/journals/trets/trets7.html#PengSMZC14
Yuan Li
Paul Chow
Jiang Jiang
Minxuan Zhang
Shaojun Wei
Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method.
1054-1059
2014
22
IEEE Trans. Very Large Scale Integr. Syst.
5
https://doi.org/10.1109/TVLSI.2013.2262103
db/journals/tvlsi/tvlsi22.html#LiCJZW14
Stuart Byma
J. Gregory Steffan
Hadi Bannazadeh
Alberto Leon-Garcia
Paul Chow
FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack.
109-116
2014
FCCM
https://doi.org/10.1109/FCCM.2014.42
https://doi.ieeecomputersociety.org/10.1109/FCCM.2014.42
conf/fccm/2014
db/conf/fccm/fccm2014.html#BymaSBLC14
Jasmina Vasiljevic
Paul Chow
MPack: global memory optimization for stream applications in high-level synthesis.
233-236
2014
FPGA
https://doi.org/10.1145/2554688.2554761
conf/fpga/2014
db/conf/fpga/fpga2014.html#VasiljevicC14
Vincent Mirian
Paul Chow
Using an OpenCL framework to evaluate interconnect implementations on FPGAs.
1-4
2014
FPL
https://doi.org/10.1109/FPL.2014.6927440
conf/fpl/2014
db/conf/fpl/fpl2014.html#MirianC14
Jasmina Vasiljevic
Paul Chow
Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use.
1-8
2014
FPL
https://doi.org/10.1109/FPL.2014.6927469
conf/fpl/2014
db/conf/fpl/fpl2014.html#VasiljevicC14
Jianfeng Zhang
Paul Chow
Hengzhu Liu
An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC.
123-130
2014
FPT
https://doi.org/10.1109/FPT.2014.7082764
conf/fpt/2014
db/conf/fpt/fpt2014.html#ZhangCL14
Ruediger Willenberg
Paul Chow
A Heterogeneous GASNet Implementation for FPGA-accelerated Computing.
2:1-2:9
2014
PGAS
https://doi.org/10.1145/2676870.2676885
conf/pgas/2014
db/conf/pgas/pgas2014.html#WillenbergC14
Stuart Byma
Hadi Bannazadeh
Alberto Leon-Garcia
J. Gregory Steffan
Paul Chow
Virtualized Reconfigurable Hardware Resources in the SAVI Testbed.
54-64
2014
TRIDENTCOM
https://doi.org/10.1007/978-3-319-13326-3_6
http://eudl.eu/doi/10.1007/978-3-319-13326-3_6
conf/tridentcom/2014
db/conf/tridentcom/tridentcom2014.html#BymaBLSC14
Ruediger Willenberg
Paul Chow
A Software Parallel Programming Approach to FPGA-Accelerated Computing.
2014
abs/1408.4959
CoRR
http://arxiv.org/abs/1408.4959
db/journals/corr/corr1408.html#WillenbergC14
Ruediger Willenberg
Paul Chow
A remote memory access infrastructure for global address space programming models in FPGAs.
211-220
2013
FPGA
https://doi.org/10.1145/2435264.2435301
conf/fpga/2013
db/conf/fpga/fpga2013.html#WillenbergC13
Stuart Byma
J. Gregory Steffan
Paul Chow
NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract.
1
2013
FPL
https://doi.org/10.1109/FPL.2013.6645624
conf/fpl/2013
db/conf/fpl/fpl2013.html#BymaSC13
Ruediger Willenberg
Paul Chow
Simulation-based HW/SW co-debugging for field-programmable systems-on-chip.
1-8
2013
FPL
https://doi.org/10.1109/FPL.2013.6645542
conf/fpl/2013
db/conf/fpl/fpl2013.html#WillenbergC13
Ruediger Willenberg
Paul Chow
SimXMD: Simulation-based HW/SW co-debugging.
1
2013
FPL
https://doi.org/10.1109/FPL.2013.6645632
conf/fpl/2013
db/conf/fpl/fpl2013.html#WillenbergC13a
Paul Chow
Why Put FPGAs in your CPU socket?
3
2013
FPT
https://doi.org/10.1109/FPT.2013.6718320
conf/fpt/2013
db/conf/fpt/fpt2013.html#Chow13
Zhongduo Lin
Paul Chow
ZCluster: A Zynq-based Hadoop cluster.
450-453
2013
FPT
https://doi.org/10.1109/FPT.2013.6718411
conf/fpt/2013
db/conf/fpt/fpt2013.html#LinC13
Manuel Saldaña
Arun Patel
Hao Jun Liu
Paul Chow
Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms.
2012
2012
Int. J. Reconfigurable Comput.
https://doi.org/10.1155/2012/127302
https://www.wikidata.org/entity/Q58689267
db/journals/ijrc/ijrc2012.html#SaldanaPLC12
127302:1-127302:10
Vincent Mirian
Paul Chow
FCache: a system for cache coherent processing on FPGAs.
233-236
2012
FPGA
https://doi.org/10.1145/2145694.2145733
conf/fpga/2012
db/conf/fpga/fpga2012.html#MirianC12
S. Alexander Chin
Paul Chow
OpenCL memory infrastructure for FPGAs (abstract only).
269-270
2012
FPGA
https://doi.org/10.1145/2145694.2145756
conf/fpga/2012
db/conf/fpga/fpga2012.html#ChinC12
Zhongduo Lin
Charles Lo
Paul Chow
K-means implementation on FPGA for high-dimensional data using triangle inequality.
437-442
2012
FPL
https://doi.org/10.1109/FPL.2012.6339141
conf/fpl/2012
db/conf/fpl/fpl2012.html#LinLC12
Vincent Mirian
Paul Chow
Managing mutex variables in a cache-coherent shared-memory system for FPGAs.
43-46
2012
FPT
https://doi.org/10.1109/FPT.2012.6412109
conf/fpt/2012
db/conf/fpt/fpt2012.html#MirianC12
Charles Lo
Paul Chow
A high-performance architecture for training Viola-Jones object detectors.
174-181
2012
FPT
https://doi.org/10.1109/FPT.2012.6412131
conf/fpt/2012
db/conf/fpt/fpt2012.html#LoC12
Yuan Li
Paul Chow
Jiang Jiang
Minxuan Zhang
Shaojun Wei
Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method.
190-197
2012
FPT
https://doi.org/10.1109/FPT.2012.6412133
conf/fpt/2012
db/conf/fpt/fpt2012.html#LiCJZW12
Ruediger Willenberg
Paul Chow
SimXMD: Integrated debugging of C code and hardware components.
309-312
2012
FPT
https://doi.org/10.1109/FPT.2012.6412154
conf/fpt/2012
db/conf/fpt/fpt2012.html#WillenbergC12
Vincent Mirian
Paul Chow
An implementation of a directory protocol for a cache coherent system on FPGAs.
1-6
2012
ReConFig
https://doi.org/10.1109/ReConFig.2012.6416731
conf/reconfig/2012
db/conf/reconfig/reconfig2012.html#MirianC12
Alexander Kaganov
Asif Lakhany
Paul Chow
FPGA Acceleration of MultiFactor CDO Pricing.
20:1-20:17
2011
4
ACM Trans. Reconfigurable Technol. Syst.
2
https://doi.org/10.1145/1968502.1968511
db/journals/trets/trets4.html#KaganovLC11
Lesley Shannon
Paul Chow
Leveraging reconfigurability in the hardware/software codesign process.
28:1-28:27
2011
4
ACM Trans. Reconfigurable Technol. Syst.
3
https://doi.org/10.1145/2000832.2000840
db/journals/trets/trets4.html#ShannonC11
Charles Lo
Paul Chow
Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI.
189-198
2011
FPGA
https://doi.org/10.1145/1950413.1950452
conf/fpga/2011
db/conf/fpga/fpga2011.html#LoC11
Yuan Li
Paul Chow
Jiang Jiang
Minxuan Zhang
Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method.
110-115
2011
FPL
https://doi.org/10.1109/FPL.2011.29
https://doi.ieeecomputersociety.org/10.1109/FPL.2011.29
conf/fpl/2011
db/conf/fpl/fpl2011.html#LiCJZ11
Yuanxi Peng
Manuel Saldaña
Paul Chow
Hardware Support for Broadcast and Reduce in MPSoC.
144-150
2011
FPL
https://doi.org/10.1109/FPL.2011.34
https://doi.ieeecomputersociety.org/10.1109/FPL.2011.34
conf/fpl/2011
db/conf/fpl/fpl2011.html#PengSC11
Paul Chow
Michael J. Wirthlin
IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011, Salt Lake City, Utah, USA, 1-3 May 2011
IEEE Computer Society
FCCM
2011
978-0-7695-4301-7
https://ieeexplore.ieee.org/xpl/conhome/5771180/proceeding
http://www.computer.org/csdl/proceedings/fccm/2011/4301/00/index.html
db/conf/fccm/fccm2011.html
Daniel Le Ly
Paul Chow
High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines.
1780-1792
2010
21
IEEE Trans. Neural Networks
11
https://doi.org/10.1109/TNN.2010.2073481
https://www.wikidata.org/entity/Q51659029
db/journals/tnn/tnn21.html#LyC10
Manuel Saldaña
Arun Patel
Christopher A. Madill
Daniel Nunes
Danyao Wang
Paul Chow
Ralph Wittig
Henry Styles
Andrew Putnam
MPI as a Programming Model for High-Performance Reconfigurable Computers.
22:1-22:29
2010
3
ACM Trans. Reconfigurable Technol. Syst.
4
https://doi.org/10.1145/1862648.1862652
db/journals/trets/trets3.html#SaldanaPMNWCWSP10
Andrew W. H. House
Manuel Saldaña
Paul Chow
Integrating High-Level Synthesis into MPI.
175-178
2010
FCCM
https://doi.org/10.1109/FCCM.2010.34
https://doi.ieeecomputersociety.org/10.1109/FCCM.2010.34
conf/fccm/2010
db/conf/fccm/fccm2010.html#HouseSC10
Dharmendra P. Gupta
Paul Chow
Acceleration of an analytical approach to collateralized debt obligation pricing.
103-106
2010
FPGA
https://doi.org/10.1145/1723112.1723130
conf/fpga/2010
db/conf/fpga/fpga2010.html#GuptaC10
Manuel Saldaña
Arun Patel
Hao Jun Liu
Paul Chow
Using Partial Reconfiguration in an Embedded Message-Passing System.
418-423
2010
ReConFig
https://doi.org/10.1109/ReConFig.2010.37
https://doi.ieeecomputersociety.org/10.1109/ReConFig.2010.37
conf/reconfig/2010
db/conf/reconfig/reconfig2010.html#SaldanaPLC10
Hadi Bannazadeh
Alberto Leon-Garcia
Keith Redmond
Gordon Tam
Arbab Khan
Mingliang Ma
Saleh Dani
Paul Chow
Virtualized Application Networking Infrastructure.
363-382
2010
TRIDENTCOM
https://doi.org/10.1007/978-3-642-17851-1_29
http://eudl.eu/doi/10.1007/978-3-642-17851-1_29
conf/tridentcom/2010
db/conf/tridentcom/tridentcom2010.html#BannazadehLRTKMDC10
Manuel Saldaña
Emanuel Ramalho
Paul Chow
A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems.
2009
2009
Int. J. Reconfigurable Comput.
https://doi.org/10.1155/2009/376232
https://www.wikidata.org/entity/Q58648048
db/journals/ijrc/ijrc2009.html#SaldanaRC09
376232:1-376232:9
Jason Luu
Keith Redmond
William Lo
Paul Chow
Lothar Lilge
Jonathan Rose
FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy.
157-164
2009
FCCM
https://doi.org/10.1109/FCCM.2009.24
https://doi.ieeecomputersociety.org/10.1109/FCCM.2009.24
conf/fccm/2009
db/conf/fccm/fccm2009.html#LuuRLCLR09
Daniel Le Ly
Paul Chow
A high-performance FPGA architecture for restricted boltzmann machines.
73-82
2009
FPGA
https://doi.org/10.1145/1508128.1508140
conf/fpga/2009
db/conf/fpga/fpga2009.html#LyC09
Daniel Le Ly
Paul Chow
A multi-FPGA architecture for stochastic Restricted Boltzmann Machines.
168-173
2009
FPL
https://doi.org/10.1109/FPL.2009.5272516
conf/fpl/2009
db/conf/fpl/fpl2009.html#LyC09
Daniel Le Ly
Manuel Saldaña
Paul Chow
The challenges of using an embedded MPI for hardware-based processing nodes.
120-127
2009
FPT
https://doi.org/10.1109/FPT.2009.5377688
conf/fpt/2009
db/conf/fpt/fpt2009.html#LySC09
Paul Chow
Manuel Saldaña
Arun Patel
Christopher A. Madill
Programming the Nallatech Xeon + multi-FPGA heterogeneous platform.
1-16
2009
Hot Chips Symposium
https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2009.7478369
conf/hotchips/2009
db/conf/hotchips/hotchips2009.html#ChowSPM09
Jiang Jiang
Vincent Mirian
Kam Pui Tang
Paul Chow
Zuocheng Xing
Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture.
48-53
2009
ReConFig
https://doi.org/10.1109/ReConFig.2009.30
https://doi.ieeecomputersociety.org/10.1109/ReConFig.2009.30
conf/reconfig/2009
db/conf/reconfig/reconfig2009.html#JiangMTCX09
Paul Chow
Peter Y. K. Cheung
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009
FPGA
ACM
2009
https://doi.org/10.1145/1508128
db/conf/fpga/fpga2009.html
978-1-60558-410-2
Tor M. Aamodt
Paul Chow
Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy.
2008
7
ACM Trans. Embed. Comput. Syst.
3
https://doi.org/10.1145/1347375.1347379
db/journals/tecs/tecs7.html#AamodtC08
26:1-26:27
Andrew W. H. House
Paul Chow
Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems.
291-292
2008
FCCM
https://doi.org/10.1109/FCCM.2008.38
https://doi.ieeecomputersociety.org/10.1109/FCCM.2008.38
conf/fccm/2008
db/conf/fccm/fccm2008.html#HouseC08
Alexander Kaganov
Paul Chow
Asif Lakhany
FPGA acceleration of Monte-Carlo based credit derivative pricing.
329-334
2008
FPL
https://doi.org/10.1109/FPL.2008.4629953
conf/fpl/2008
db/conf/fpl/fpl2008.html#KaganovCL08
Daniel Nunes
Manuel Saldaña
Paul Chow
A profiler for a heterogeneous multi-core multi-FPGA system.
113-120
2008
FPT
https://doi.org/10.1109/FPT.2008.4762373
conf/fpt/2008
db/conf/fpt/fpt2008.html#NunesSC08
Manuel Saldaña
Emanuel Ramalho
Paul Chow
A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI.
265-270
2008
ReConFig
https://doi.org/10.1109/ReConFig.2008.10
https://doi.ieeecomputersociety.org/10.1109/ReConFig.2008.10
conf/reconfig/2008
db/conf/reconfig/reconfig2008.html#SaldanaRC08
Manuel Saldaña
Arun Patel
Christopher A. Madill
Daniel Nunes
Danyao Wang
Henry Styles
Andrew Putnam
Ralph Wittig
Paul Chow
MPI as an abstraction for software-hardware interaction for HPRCs.
1-10
2008
HPRCTA@SC
https://doi.org/10.1109/HPRCTA.2008.4745682
conf/sc/2008hprcta
db/conf/sc/hprcta2008.html#SaldanaPMNWSPWC08
Mike Hutton
Paul Chow
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008
FPGA
ACM
2008
https://doi.org/10.1145/1344671
db/conf/fpga/fpga2008.html
978-1-59593-934-0
Lesley Shannon
Paul Chow
SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse.
377-390
2007
15
IEEE Trans. Very Large Scale Integr. Syst.
4
https://doi.org/10.1109/TVLSI.2007.893645
db/journals/tvlsi/tvlsi15.html#ShannonC07
Manuel Saldaña
Lesley Shannon
Jia Shuo Yue
Sikang Bian
John Craig
Paul Chow
Routability of Network Topologies in FPGAs.
948-951
2007
15
IEEE Trans. Very Large Scale Integr. Syst.
8
https://doi.org/10.1109/TVLSI.2007.900746
db/journals/tvlsi/tvlsi15.html#SaldanaSYBCC07
Samir Parikh
P. Glenn Gulak
Paul Chow
A CMOS Image Sensor for DNA Microarrays.
821-824
2007
CICC
https://doi.org/10.1109/CICC.2007.4405854
conf/cicc/2007
db/conf/cicc/cicc2007.html#ParikhGC07
Sam Lee
Paul Chow
An FPGA Implementation of Reciprocal Sums for SPME.
159-165
2007
conf/ersa/2007
ERSA
db/conf/ersa/ersa2007.html#LeeC07
Paul Chow
Mike Hutton
Integrating FPGAs in high-performance computing: introduction.
131
2007
conf/fpga/2007
FPGA
https://doi.org/10.1145/1216919.1216940
db/conf/fpga/fpga2007.html#ChowH07
Chichyang Chen
Paul Chow
Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor.
540-545
2007
conf/glvlsi/2007
ACM Great Lakes Symposium on VLSI
https://doi.org/10.1145/1228784.1228912
db/conf/glvlsi/glvlsi2007.html#ChenC07
Tor M. Aamodt
Paul Chow
Optimization of data prefetch helper threads with path-expression based statistical modeling.
210-221
2007
conf/ics/2007
ICS
https://doi.org/10.1145/1274971.1275001
db/conf/ics/ics2007.html#AamodtC07
Arun Patel
Christopher A. Madill
Manuel Saldaña
Chris Comis
Régis Pomès
Paul Chow
A Scalable FPGA-based Multiprocessor.
111-120
2006
conf/fccm/2006
FCCM
https://doi.org/10.1109/FCCM.2006.17
https://doi.ieeecomputersociety.org/10.1109/FCCM.2006.17
db/conf/fccm/fccm2006.html#PatelMSCPC06
Manuel Saldaña
Lesley Shannon
Paul Chow
The routability of multiprocessor network topologies in FPGAs.
232
2006
conf/fpga/2006
FPGA
https://doi.org/10.1145/1117201.1117253
db/conf/fpga/fpga2006.html#SaldanaSC06
Manuel Saldaña
Paul Chow
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs.
1-6
2006
conf/fpl/2006
FPL
https://doi.org/10.1109/FPL.2006.311233
db/conf/fpl/fpl2006.html#SaldanaC06
Lesley Shannon
Blair Fort
Samir Parikh
Arun Patel
Manuel Saldaña
Paul Chow
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification.
1-6
2006
conf/fpl/2006
FPL
https://doi.org/10.1109/FPL.2006.311227
db/conf/fpl/fpl2006.html#ShannonFPPSC06
Manuel Saldaña
Daniel Nunes
Emanuel Ramalho
Paul Chow
Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI.
260-279
2006
ReConFig
https://doi.org/10.1109/RECONF.2006.307779
https://doi.ieeecomputersociety.org/10.1109/RECONF.2006.307779
conf/reconfig/2006
db/conf/reconfig/reconfig2006.html#SaldanaNRC06
Manuel Saldaña
Lesley Shannon
Paul Chow
The routability of multiprocessor network topologies in FPGAs.
49-56
2006
conf/slip/2006
SLIP
https://doi.org/10.1145/1117278.1117290
db/conf/slip/slip2006.html#SaldanaSC06
Lesley Shannon
Paul Chow
Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller.
63-72
2005
conf/fccm/2005
FCCM
https://doi.org/10.1109/FCCM.2005.59
https://doi.ieeecomputersociety.org/10.1109/FCCM.2005.59
db/conf/fccm/fccm2005.html#ShannonC05
Lesley Shannon
Paul Chow
Leveraging Reconfigurability in the Design Process.
731-732
2005
conf/fpl/2005
FPL
db/conf/fpl/fpl2005.html#ShannonC05
https://doi.org/10.1109/FPL.2005.1515830
https://doi.ieeecomputersociety.org/10.1109/FPL.2005.1515830
Lesley Shannon
Blair Fort
Samir Parikh
Arun Patel
Manuel Saldaña
Paul Chow
Designing an FPGA SoC Using a Standardized IP Block Interface.
341-342
2005
conf/fpt/2005
FPT
db/conf/fpt/fpt2005.html#ShannonFPPSC05
Navid Azizi
Ian Kuon
Aaron Egier
Ahmad Darabiha
Paul Chow
Reconfigurable Molecular Dynamics Simulator.
197-206
2004
conf/fccm/2004
FCCM
https://doi.org/10.1109/FCCM.2004.48
https://doi.ieeecomputersociety.org/10.1109/FCCM.2004.48
db/conf/fccm/fccm2004.html#AziziKEDC04
Lesley Shannon
Paul Chow
Using reconfigurability to achieve real-time profiling for hardware/software codesign.
190-199
2004
conf/fpga/2004
FPGA
https://doi.org/10.1145/968280.968308
db/conf/fpga/fpga2004.html#ShannonC04
Ian Kuon
Navid Azizi
Ahmad Darabiha
Aaron Egier
Paul Chow
FPGA-based supercomputing: an implementation for molecular dynamics.
253
2004
conf/fpga/2004
FPGA
https://doi.org/10.1145/968280.968340
db/conf/fpga/fpga2004.html#KuonADEC04
Lesley Shannon
Paul Chow
Maximizing system performance: using reconfigurability to monitor system communications.
231-238
2004
FPT
https://doi.org/10.1109/FPT.2004.1393273
conf/fpt/2004
db/conf/fpt/fpt2004.html#ShannonC04
Tor M. Aamodt
Paul Chow
Per Hammarlund
Hong Wang 0003
John Paul Shen
Hardware Support for Prescient Instruction Prefetch.
84-95
2004
conf/hpca/2004
HPCA
https://doi.org/10.1109/HPCA.2004.10028
https://doi.ieeecomputersociety.org/10.1109/HPCA.2004.10028
db/conf/hpca/hpca2004.html#AamodtCHWS04
Lesley Shannon
Paul Chow
Standardizing the Performance Assessment of Reconfigurable Processor Architectures.
282-283
2003
conf/fccm/2003
FCCM
https://doi.org/10.1109/FPGA.2003.1227271
https://doi.ieeecomputersociety.org/10.1109/FPGA.2003.1227271
db/conf/fccm/fccm2003.html#ShannonC03
Tor M. Aamodt
Pedro Marcuello
Paul Chow
Antonio González 0001
Per Hammarlund
Hong Wang 0003
John Paul Shen
A framework for modeling and optimization of prescient instruction prefetch.
13-24
2003
conf/sigmetrics/2003
SIGMETRICS
https://doi.org/10.1145/781027.781030
https://doi.org/10.1145/885651.781030
db/conf/sigmetrics/sigmetrics2003.html#AamodtMCGHWS03
Jorge E. Carrillo
Paul Chow
The effect of reconfigurable units in superscalar processors.
141-150
2001
conf/fpga/2001
FPGA
https://doi.org/10.1145/360276.360328
db/conf/fpga/fpga2001.html#CarrilloC01
L. Louis Zhang
Brent Beacham
Massoud R. Hashemi
Paul Chow
Alberto Leon-Garcia
A Scheduler ASIC for a Programmable Packet Switch.
42-48
2000
20
IEEE Micro
1
https://doi.org/10.1109/40.820052
http://doi.ieeecomputersociety.org/10.1109/40.820052
db/journals/micro/micro20.html#ZhangBHCL00
Tor M. Aamodt
Paul Chow
Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation.
128-137
2000
conf/cases/2000
CASES
https://doi.org/10.1145/354880.354899
db/conf/cases/cases2000.html#AamodtC00
Keith I. Farkas
Paul Chow
Norman P. Jouppi
Zvonko G. Vranesic
The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning.
327-356
1999
27
Int. J. Parallel Program.
5
db/journals/ijpp/ijpp27.html#FarkasCJV99
https://doi.org/10.1023/A:1018782806674
Paul Chow
Soon Ong Seo
Jonathan Rose
Kevin Chung
Gerard Páez-Monzón
Immanuel Rahardja
The design of an SRAM-based field-programmable gate array. I. Architecture.
191-197
1999
7
IEEE Trans. Very Large Scale Integr. Syst.
2
https://doi.org/10.1109/92.766746
db/journals/tvlsi/tvlsi7.html#ChowSRCPR99
Paul Chow
Soon Ong Seo
Jonathan Rose
Kevin Chung
Gerard Páez-Monzón
Immanuel Rahardja
The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout.
321-330
1999
7
IEEE Trans. Very Large Scale Integr. Syst.
3
https://doi.org/10.1109/92.784093
db/journals/tvlsi/tvlsi7.html#ChowSRCPR99a
Ivan Hamer
Paul Chow
DES Cracking on the Transmogrifier 2a.
13-24
https://doi.org/10.1007/3-540-48059-5_3
1999
conf/ches/1999
CHES
db/conf/ches/ches1999.html#HamerC99
Jeffrey A. Jacob
Paul Chow
Memory Interfacing and Instruction Specification for Reconfigurable Processors.
145-154
1999
conf/fpga/1999
FPGA
https://doi.org/10.1145/296399.296446
db/conf/fpga/fpga99.html#JacobC99
David M. Lewis
David R. Galloway
Marcus van Ierssel
Jonathan Rose
Paul Chow
The Transmogrifier-2: a 1 million gate rapid-prototyping system.
188-198
1998
6
IEEE Trans. Very Large Scale Integr. Syst.
2
https://doi.org/10.1109/92.678867
db/journals/tvlsi/tvlsi6.html#LewisGIRC98
David M. Lewis
David R. Galloway
Marcus van Ierssel
Jonathan Rose
Paul Chow
The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System.
53-61
1997
conf/fpga/1997
FPGA
https://doi.org/10.1145/258305.258312
db/conf/fpga/fpga97.html#LewisGIRC97
Keith I. Farkas
Paul Chow
Norman P. Jouppi
Zvonko G. Vranesic
Memory-System Design Considerations for Dynamically-Scheduled Processors.
133-143
1997
conf/isca/1997
ISCA
https://doi.org/10.1145/264107.264156
https://doi.ieeecomputersociety.org/10.1109/ISCA.1997.604628
db/conf/isca/isca97.html#FarkasCJV97
Keith I. Farkas
Paul Chow
Norman P. Jouppi
Zvonko G. Vranesic
The Multicluster Architecture: Reducing Cycle Time Through Partitioning.
149-159
1997
conf/micro/1997
MICRO
https://doi.org/10.1109/MICRO.1997.645806
https://doi.ieeecomputersociety.org/10.1109/MICRO.1997.645806
https://dl.acm.org/doi/10.5555/266800.266815
db/conf/micro/micro97.html#FarkasCJV97
Mazen A. R. Saghir
Paul Chow
Corinna G. Lee
Exploiting Dual Data-Memory Banks in Digital Signal Processors.
234-243
1996
conf/asplos/1996
ASPLOS
db/conf/asplos/asplos96.html#SaghirCL96
https://doi.org/10.1145/237090.237193
https://doi.org/10.1145/248209.237193
https://doi.org/10.1145/248208.237193
David Yeh
Gennady Feygin
Paul Chow
RACER: a reconfigurable constraint-length 14 Viterbi decoder.
60-69
1996
FCCM
https://doi.org/10.1109/FPGA.1996.564746
conf/fccm/1996
db/conf/fccm/fccm1996.html#YehFC96
Ralph Wittig
Paul Chow
OneChip: an FPGA processor with reconfigurable logic.
126-135
1996
FCCM
https://doi.org/10.1109/FPGA.1996.564773
conf/fccm/1996
db/conf/fccm/fccm1996.html#WittigC96
Keith I. Farkas
Norman P. Jouppi
Paul Chow
Register File Design Considerations in Dynamically Scheduled Processors.
40-51
1996
conf/hpca/1996
HPCA
https://doi.org/10.1109/HPCA.1996.501172
https://doi.ieeecomputersociety.org/10.1109/HPCA.1996.501172
db/conf/hpca/hpca1996.html#FarkasJC96
Paul Chow
P. Glenn Gulak
A Field-Programmable Mixed-Analog-Digital Array.
104-109
1995
conf/fpga/1995
FPGA
https://doi.org/10.1145/201310.201327
db/conf/fpga/fpga95.html#ChowGC95
Keith I. Farkas
Norman P. Jouppi
Paul Chow
How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?
78-89
1995
conf/hpca/1995
HPCA
db/conf/hpca/hpca1995.html#FarkasJC95
https://doi.org/10.1109/HPCA.1995.386553
https://doi.ieeecomputersociety.org/10.1109/HPCA.1995.386553
Gennady Feygin
P. Glenn Gulak
Paul Chow
Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding.
805-816
1994
30
Inf. Process. Manag.
6
db/journals/ipm/ipm30.html#FeyginGC94
https://doi.org/10.1016/0306-4573(94)90008-6
Gennady Feygin
P. Glenn Gulak
Paul Chow
Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression.
254-263
1994
conf/dcc/1994
Data Compression Conference
db/conf/dcc/dcc94.html#FeyginGC94
https://doi.org/10.1109/DCC.1994.305933
Mazen A. R. Saghir
Paul Chow
Corinna G. Lee
Application-driven design of DSP architectures and compilers.
437-440
1994
ICASSP (2)
https://doi.org/10.1109/ICASSP.1994.389627
https://doi.ieeecomputersociety.org/10.1109/ICASSP.1994.389627
conf/icassp/1994
db/conf/icassp/icassp1994.html#SaghirCL94
Gennady Feygin
Patrick Glenn Gulak
Paul Chow
A multiprocessor architecture for Viterbi decoders with linear speedup.
2907-2917
1993
41
IEEE Trans. Signal Process.
9
https://doi.org/10.1109/78.236512
db/journals/tsp/tsp41.html#FeyginGC93
Gennady Feygin
P. Glenn Gulak
Paul Chow
Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding.
118-127
1993
conf/dcc/1993
Data Compression Conference
db/conf/dcc/dcc93.html#FeyginGC93
https://doi.org/10.1109/DCC.1993.253138
Gennady Feygin
Paul Chow
P. Glenn Gulak
John Chappel
Grant Goodes
Oswin Hall
Ahmad Sayes
Satwant Singh
Michael B. Smith
Steven J. E. Wilton
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.
1945-1948
1993
conf/iscas/1993
ISCAS
db/conf/iscas/iscas1993-3.html#FeyginCGCGHSSSW93
Gennady Feygin
Patrick Glenn Gulak
Paul Chow
Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up.
1097-1100
1991
ICASSP
https://doi.org/10.1109/ICASSP.1991.150554
conf/icassp/1991
db/conf/icassp/icassp1991.html#FeyginGC91
Michael Takefman
Paul Chow
A streamlined DSP microprocessor architecture.
1257-1260
1991
ICASSP
https://doi.org/10.1109/ICASSP.1991.150624
conf/icassp/1991
db/conf/icassp/icassp1991.html#TakefmanC91
Paul Chow
Mark Horowitz
Architectural Tradeoffs in the Design of MIPS-X.
300-308
1987
conf/isca/1987
ISCA
db/conf/isca/isca87.html#ChowH87
https://doi.org/10.1145/30350.30384
Paul Chow
Zvonko G. Vranesic
Jui Lin Yen
A Pipelined Distributed Arithmetic PFFT Processor.
1128-1136
1983
32
IEEE Trans. Computers
12
db/journals/tc/tc32.html#ChowVY83
https://doi.org/10.1109/TC.1983.1676173
http://doi.ieeecomputersociety.org/10.1109/TC.1983.1676173
Tor M. Aamodt
Mustafa Abbas
Yasmin Afsharnejad
Shawki Areibi
Navid Azizi
Hadi Bannazadeh
Brent Beacham
Vaughn Betz
Sikang Bian
Christophe Bobda
Andrew Boutros
Stuart Byma
Fernando Martin del Campo
Jorge E. Carrillo
John Chappel
Chichyang Chen
Peter Y. K. Cheung
S. Alexander Chin
Kevin Chung
Chris Comis
John Craig
Saleh Dani
Ahmad Darabiha
Roberto DiCecco
Yong Dou
Aaron Egier
Kenneth EguroKen Eguro
Geoffrey Elliott
Nariman Eskandari
Mohammad Ewais
Keith I. Farkas
Gennady Feygin
Jeff Fifield
Blair Fort
Eric Fukuda
David R. Galloway
Yu Gao
Ehsan Ghasemi
Antonio González 0001
Grant Goodes
Brett Grady
Giuseppe Di Guglielmo
P. Glenn GulakPatrick Glenn Gulak
Dharmendra P. Gupta
Oswin Hall
Ivan Hamer
Per Hammarlund
Suranga Handagala
Philip C. Harris
Massoud R. Hashemi
Martin C. Herbordt
H. Peter Hofstee
Mark Horowitz
Andrew W. H. House
Mike Hutton
Marcus van Ierssel
Jeffrey A. Jacob
Hans-Arno Jacobsen
Jiang Jiang
Jingfei Jiang
Tian Jiang
Norman P. Jouppi
Alexander Kaganov
Arbab Khan
Dirk Koch
Jeffrey D. Krupa
Ian Kuon
Griffin Lacey
Asif Lakhany
Corinna G. Lee
Sam Lee
Miriam Leeser
Alberto Leon-Garcia
David M. Lewis
Jun Li 0094
Yuan Li
Lothar Lilge
Thomas Lin
Zhongduo Lin
David Lion
Hao Jun Liu
Hengzhu Liu
Zhiqiang Liu
Charles Lo
William Lo
Vladimir Loncar
Jason Luu
Daniel Le Ly
Daniel Ly-Ma
Mingliang Ma
Christopher A. Madill
Joel MandebiJoel Mandebi Mbongue
Pedro Marcuello
Fernando Martinez-Vallina
Mohammadmahdi Mazraeli
Marco Antonio Merlini
Vincent Mirian
Daniel Nunes
Gerard Páez-Monzón
Samir Parikh
Byungchul Park
Arun Patel
Yuanxi Peng
Marco Platzner
Christian Plessl
Régis Pomès
Isamu Poy
Andrew Putnam
Arzhang Rafii
Omar Ragheb
Immanuel Rahardja
Emanuel Ramalho
Dylan S. Rankin
Keith Redmond
Burkhard Ringlein
Jonathan Rose
Daniel Rozhko
Mazen A. R. Saghir
Manuel Saldaña
Ahmed Sanaullah
Ahmad Sayes
Paul Schumacher
Soon Ong Seo
Hafsah Shahzad
Lesley Shannon
Varun Sharma
John Paul Shen
Qianfeng ShenQianfeng Clark Shen
Satwant Singh
Michael B. Smith
J. Gregory Steffan
Henry Styles
Lin Sun
Welson Sun
Jakub Szefer
Michael Takefman
Gordon Tam
Kam Pui Tang
Naif Tarafdar
Graham W. Taylor
Russell Tessier
Nhan Tran
Jasmina Vasiljevic
Juan Camilo Vega
Zvonko G. Vranesic
Danyao Wang
Hong Wang 0003
Qiang Wang 0006
Shaojun Wei
Ruediger Willenberg
Steve WiltonSteven J. E. Wilton
Michael J. Wirthlin
Ralph Wittig
Zhenbin Wu
Zuocheng Xing
Talia Xu
Abdul-Amir Yassine
David Yeh
Jui Lin Yen
Jia Shuo Yue
Jianfeng Zhang
L. Louis Zhang
Minxuan Zhang
Jun Zheng
Xiaofeng Zou